soc/qualcomm/x1p42100: Add PCIE Clock support for x1p42100
Add support to enable PCIE NOC, Controller and PHY clocks. The register details are part of HRD-X1P42100-S1 document. https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/ TEST=Create an image.serial.bin, ensure it boots on X1P42100 and check clock status Change-Id: I6007a8315343a2d56d51c8472ace831a10146768 Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
haril
Matt DeVillier
parent
4d3def7514
commit
1b8dd662a9
5 changed files with 454 additions and 13 deletions
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@ -40,6 +40,7 @@ ramstage-y += soc.c
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ramstage-y += cbmem.c
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ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
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ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
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ramstage-$(CONFIG_PCI) += pcie.c
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ramstage-y += cpucp_load_reset.c
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################################################################################
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@ -79,6 +79,169 @@ static struct clock_freq_config qupv3_wrap_cfg[] = {
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},
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};
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static u32 *gdsc[MAX_GDSC] = {
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[PCIE_6A_GDSC] = &gcc->pcie_6a.gdscr,
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[PCIE_6_PHY_GDSC] = &gcc->pcie_6_phy_gdscr,
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};
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struct pcie pcie_cfg[] = {
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[PCIE_6A_GDSC] = {
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.gdscr = &gcc->pcie_6a.gdscr,
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},
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[ANOC_PCIE_AT_CBCR] = {
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.clk = &gcc->pcie_noc.anoc_pcie_at_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en2,
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.vote_bit = ANOC_PCIE_AT_CLK_ENA,
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},
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[ANOC_PCIE_QOSGEN_EXTREF_CBCR] = {
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.clk = &gcc->pcie_noc.anoc_pcie_qosgen_extref_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en2,
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.vote_bit = ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA,
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},
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[DDRSS_PCIE_SF_QTB_CBCR] = {
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.clk = &gcc->pcie_noc.ddrss_pcie_sf_qtb_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en,
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.vote_bit = DDRSS_PCIE_SF_QTB_CLK_ENA,
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},
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[CNOC_PCIE_NORTH_SF_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.cnoc_pcie_north_sf_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en1,
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.vote_bit = CNOC_PCIE_NORTH_SF_AXI_CLK_ENA,
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},
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[CNOC_PCIE_SOUTH_SF_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.cnoc_pcie_south_sf_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = CNOC_PCIE_SOUTH_SF_AXI_CLK_ENA,
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},
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[NOC_PCIE_DCD_XO_CBCR] = {
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.clk = &gcc->pcie_noc.noc_pcie_dcd_xo_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = NOC_PCIE_DCD_XO_CLK_ENA,
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},
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[NOC_PCIE_SOUTH_DCD_XO_CBCR] = {
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.clk = &gcc->pcie_noc.noc_pcie_south_dcd_xo_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = NOC_PCIE_SOUTH_DCD_XO_CLK_ENA,
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},
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[NOC_PCIE_NORTH_DCD_XO_CBCR] = {
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.clk = &gcc->pcie_noc.noc_pcie_north_dcd_xo_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en1,
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.vote_bit = NOC_PCIE_NORTH_DCD_XO_CLK_ENA,
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},
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[CFG_NOC_PCIE_ANOC_AHB_CBCR] = {
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.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_ahb_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = CFG_NOC_PCIE_ANOC_AHB_CLK_ENA,
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},
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[CFG_NOC_PCIE_ANOC_NORTH_AHB_CBCR] = {
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.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_north_ahb_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK_ENA,
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},
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[CFG_NOC_PCIE_ANOC_SOUTH_AHB_CBCR] = {
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.clk = &gcc->pcie_noc.cfg_noc_pcie_anoc_south_ahb_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en,
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.vote_bit = CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK_ENA,
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},
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[AGGRE_NOC_PCIE_NORTH_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.aggre_noc_pcie_north_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = AGGRE_NOC_PCIE_NORTH_AXI_CLK_ENA,
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},
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[ANOC_PCIE_PWRCTL_CBCR] = {
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.clk = &gcc->pcie_noc.anoc_pcie_pwrctl_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en1,
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.vote_bit = ANOC_PCIE_PWRCTL_CLK_ENA,
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},
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[AGGRE_NOC_PCIE_SOUTH_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.aggre_noc_pcie_south_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = AGGRE_NOC_PCIE_SOUTH_AXI_CLK_ENA,
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},
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[AGGRE_NOC_PCIE_HS_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = AGGRE_NOC_PCIE_HS_AXI_CLK_ENA,
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},
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[AGGRE_NOC_PCIE_HS_NORTH_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_north_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = AGGRE_NOC_PCIE_HS_NORTH_AXI_CLK_ENA,
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},
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[AGGRE_NOC_PCIE_HS_SOUTH_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.aggre_noc_pcie_hs_south_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en5,
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.vote_bit = AGGRE_NOC_PCIE_HS_SOUTH_AXI_CLK_ENA,
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},
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[CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.cnoc_pcie_north_sf_tunnel_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en2,
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.vote_bit = CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CLK_ENA,
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},
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[CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CBCR] = {
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.clk = &gcc->pcie_noc.cnoc_pcie_south_sf_tunnel_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en2,
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.vote_bit = CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CLK_ENA,
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},
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[PCIE_6A_SLV_Q2A_AXI_CLK] = {
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.clk = &gcc->pcie_6a.slv_q2a_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_SLV_Q2A_AXI_CLK_ENA,
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},
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[PCIE_6A_SLV_AXI_CLK] = {
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.clk = &gcc->pcie_6a.slv_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_SLV_AXI_CLK_ENA,
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},
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[PCIE_6A_MSTR_AXI_CLK] = {
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.clk = &gcc->pcie_6a.mstr_axi_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_MSTR_AXI_CLK_ENA,
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},
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[PCIE_6A_CFG_AHB_CLK] = {
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.clk = &gcc->pcie_6a.cfg_ahb_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_CFG_AHB_CLK_ENA,
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},
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[PCIE_6A_AUX_CLK] = {
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.clk = &gcc->pcie_6a.aux_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_AUX_CLK_ENA,
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},
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[PCIE_6A_PHY_AUX_CLK] = {
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.clk = &gcc->pcie_6a.phy_aux_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_PHY_AUX_CLK_ENA,
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},
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[PCIE_6A_PHY_RCHNG_CLK] = {
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.clk = &gcc->pcie_6a.phy_rchng_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_PHY_RCHNG_CLK_ENA,
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},
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[PCIE_6A_PIPE_CLK] = {
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.clk = &gcc->pcie_6a.pipe_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_PIPE_CLK_ENA,
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},
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[PCIE_6A_PIPEDIV2_CLK] = {
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.clk = &gcc->pcie_6a.pipediv2_cbcr,
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.clk_br_en = &gcc->apcs_clk_br_en3,
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.vote_bit = PCIE_6A_PIPEDIV2_CLK_ENA,
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},
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[PCIE_6A_PIPE_MUXR] = {
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.clk = &gcc->pcie_6a.pipe_muxr,
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.vote_bit = NO_VOTE_BIT,
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},
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};
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static struct clock_freq_config pcie_core_cfg[] = {
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{
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.hz = 100 * MHz,
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.src = SRC_GPLL0_MAIN_600MHZ,
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.div = QCOM_CLOCK_DIV(6),
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},
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};
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void clock_configure_qspi(uint32_t hz)
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{
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clock_configure(&gcc->qspi_core, qspi_core_cfg, hz, ARRAY_SIZE(qspi_core_cfg));
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@ -134,6 +297,48 @@ static enum cb_err clock_configure_gpll0(void)
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return clock_configure_enable_gpll(&gpll0_cfg, false, 0);
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}
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enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type)
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{
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if (gdsc_type > MAX_GDSC)
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return CB_ERR;
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return enable_and_poll_gdsc_status(gdsc[gdsc_type]);
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}
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enum cb_err clock_enable_pcie(enum clk_pcie clk_type)
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{
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int clk_vote_bit;
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if (clk_type >= PCIE_CLK_COUNT)
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return CB_ERR;
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clk_vote_bit = pcie_cfg[clk_type].vote_bit;
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if (clk_vote_bit < 0)
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return clock_enable(pcie_cfg[clk_type].clk);
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return clock_enable_vote(pcie_cfg[clk_type].clk,
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pcie_cfg[clk_type].clk_br_en, pcie_cfg[clk_type].vote_bit);
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}
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enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type)
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{
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if (clk_type >= PCIE_CLK_COUNT)
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return CB_ERR;
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/* Set clock src */
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write32(pcie_cfg[clk_type].clk, src_type);
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return CB_SUCCESS;
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}
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void clock_configure_pcie(void)
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{
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clock_configure(&gcc->pcie_6a.phy_rchng_rcg,
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pcie_core_cfg, PCIE_PHY_RCHNG_FREQ, ARRAY_SIZE(pcie_core_cfg));
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}
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static void speed_up_boot_cpu(void)
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{
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/* Placeholder */
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@ -59,4 +59,46 @@
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#define QUP_WRAP2_BASE 0x008C0000
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#define QUP_2_GSI_BASE 0x00804000
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/* PCIE 6A */
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#define PCIE6A_PCIE_PARF 0x01BF8000
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#define PCIE6A_GEN1X4_PCIE_DBI 0x70000000
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#define PCIE6A_GEN1X4_PCIE_ELBI 0x70000F40
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#define PCIE6A_GEN1X4_DWC_PCIE_DM_IATU 0x70001000
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#define PCIE6A_SPACE_END_ADDR 0x74000000
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#define PCIE6A_BCR 0x131000
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#define GCC_PCIE_6A_PHY_BCR 0x1AC01C
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/* QMP PHY, Serdes,Tx, Rx and PCS register definitions */
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#define PCIE_6A_AQMP_PHY 0x01BFC000
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#define PCIE_6A_BQMP_PHY 0x01BFE000
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#define PCIE6A_AQPHY_TX0 0x01BFC000
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#define PCIE6A_AQPHY_RX0 0x01BFC200
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#define PCIE6A_AQPHY_TX1 0x01BFC800
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#define PCIE6A_AQPHY_RX1 0x01BFCA00
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#define PCIE6A_AQPHY_LN_SHRD 0x01BFCE00
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#define PCIE6A_AQPHY_SERDES 0x01BFD000
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#define PCIE6A_AQPHY_PCS_COM 0x01BFD200
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#define PCIE6A_AQPHY_PCS_PCIE 0x01BFD400
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#define PCIE6A_AQPHY_PCS_LANE0 0x01BFD800
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#define PCIE6A_AQPHY_PCS_PCIE_LANE0 0x01BFDA00
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#define PCIE6A_AQPHY_PCS_LANE1 0x01BFDC00
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#define PCIE6A_AQPHY_PCS_PCIE_LANE1 0x01BFDE00
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#define PCIE6A_BQPHY_TX0 0x01BFE000
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#define PCIE6A_BQPHY_RX0 0x01BFE200
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#define PCIE6A_BQPHY_TX1 0x01BFE800
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#define PCIE6A_BQPHY_RX1 0x01BFEA00
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#define PCIE6A_BQPHY_LN_SHRD 0x01BFEE00
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#define PCIE6A_BQPHY_SERDES 0x01BFF000
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#define PCIE6A_BQPHY_PCS_COM 0x01BFF200
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#define PCIE6A_BQPHY_PCS_PCIE 0x01BFF400
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#define PCIE6A_BQPHY_PCS_LANE0 0x01BFF800
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#define PCIE6A_BQPHY_PCS_PCIE_LANE0 0x01BFFA00
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#define PCIE6A_BQPHY_PCS_LANE1 0x01BFFC00
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#define PCIE6A_BQPHY_PCS_PCIE_LANE1 0x01BFFE00
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/* TCSR */
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#define TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE ((void *)0x1FD512C)
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#endif /* __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
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@ -13,6 +13,8 @@
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#define GPLL0_MAIN_HZ (600 * MHz)
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#define CLK_100MHZ (100 * MHz)
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#define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
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#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
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#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
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#define QUPV3_WRAP2_CLK_ENA_S(idx) (4 + idx)
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@ -50,6 +52,35 @@ enum apcs_branch_en_vote {
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QUPV3_WRAP2_CORE_CLK_ENA = 0,
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QUPV3_WRAP_2_M_AHB_CLK_ENA = 2,
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QUPV3_WRAP_2_S_AHB_CLK_ENA = 1,
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ANOC_PCIE_AT_CLK_ENA = 11,
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ANOC_PCIE_QOSGEN_EXTREF_CLK_ENA = 13,
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DDRSS_PCIE_SF_QTB_CLK_ENA = 19,
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CNOC_PCIE_NORTH_SF_AXI_CLK_ENA = 6,
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CNOC_PCIE_SOUTH_SF_AXI_CLK_ENA = 12,
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NOC_PCIE_DCD_XO_CLK_ENA = 24,
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NOC_PCIE_SOUTH_DCD_XO_CLK_ENA = 25,
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NOC_PCIE_NORTH_DCD_XO_CLK_ENA = 29,
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CFG_NOC_PCIE_ANOC_AHB_CLK_ENA = 20,
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CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK_ENA = 22,
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CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK_ENA = 20,
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AGGRE_NOC_PCIE_NORTH_AXI_CLK_ENA = 19,
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ANOC_PCIE_PWRCTL_CLK_ENA = 31,
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AGGRE_NOC_PCIE_SOUTH_AXI_CLK_ENA = 13,
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AGGRE_NOC_PCIE_HS_AXI_CLK_ENA = 14,
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AGGRE_NOC_PCIE_HS_NORTH_AXI_CLK_ENA = 15,
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AGGRE_NOC_PCIE_HS_SOUTH_AXI_CLK_ENA = 16,
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CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CLK_ENA = 14,
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CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CLK_ENA = 15,
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PCIE_6A_SLV_Q2A_AXI_CLK_ENA = 20,
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PCIE_6A_SLV_AXI_CLK_ENA = 21,
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PCIE_6A_MSTR_AXI_CLK_ENA = 22,
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PCIE_6A_CFG_AHB_CLK_ENA = 23,
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PCIE_6A_AUX_CLK_ENA = 24,
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PCIE_6A_PHY_AUX_CLK_ENA = 25,
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PCIE_6A_PIPE_CLK_ENA = 26,
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PCIE_6A_PHY_RCHNG_CLK_ENA = 27,
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PCIE_6A_PIPEDIV2_CLK_ENA = 28,
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NO_VOTE_BIT = -1,
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};
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struct x1p42100_gpll {
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@ -66,9 +97,68 @@ struct x1p42100_gpll {
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u32 config_ctl_u1;
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};
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struct x1p42100_pcie_noc {
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u32 anoc_pcie_at_cbcr;
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u32 anoc_pcie_tsctr_cbcr;
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u32 anoc_pcie_qosgen_extref_cbcr;
|
||||
u32 ddrss_pcie_sf_qtb_cbcr;
|
||||
u32 cnoc_pcie_north_sf_axi_cbcr;
|
||||
u32 cnoc_pcie_south_sf_axi_cbcr;
|
||||
u32 noc_pcie_north_dcd_xo_cbcr;
|
||||
u32 noc_pcie_dcd_xo_cbcr;
|
||||
u32 noc_pcie_south_dcd_xo_cbcr;
|
||||
u32 cfg_noc_pcie_anoc_ahb_cbcr;
|
||||
u32 cfg_noc_pcie_anoc_north_ahb_cbcr;
|
||||
u32 cfg_noc_pcie_anoc_south_ahb_cbcr;
|
||||
u32 aggre_noc_pcie_north_axi_cbcr;
|
||||
u32 anoc_pcie_pwrctl_cbcr;
|
||||
u32 aggre_noc_pcie_south_axi_cbcr;
|
||||
u32 aggre_noc_pcie_hs_axi_cbcr;
|
||||
u32 aggre_noc_pcie_hs_north_axi_cbcr;
|
||||
u32 aggre_noc_pcie_hs_south_axi_cbcr;
|
||||
u32 cnoc_pcie_north_sf_tunnel_axi_cbcr;
|
||||
u32 cnoc_pcie_south_sf_tunnel_axi_cbcr;
|
||||
};
|
||||
|
||||
struct x1p42100_pcie {
|
||||
u32 bcr;
|
||||
u32 gdscr;
|
||||
u8 _res0[0x131018 - 0x131008];
|
||||
u32 slv_q2a_axi_cbcr;
|
||||
u32 slv_axi_cbcr;
|
||||
u8 _res1[0x131028 - 0x131020];
|
||||
u32 mstr_axi_cbcr;
|
||||
u8 _res2[0x131034 - 0x13102c];
|
||||
u32 cfg_ahb_cbcr;
|
||||
u32 aux_cbcr;
|
||||
u8 _res3[0x131044 - 0x13103c];
|
||||
u32 phy_aux_cbcr;
|
||||
u8 _res4[0x131050 - 0x131048];
|
||||
u32 pipe_cbcr;
|
||||
u8 _res5[0x13105c - 0x131054];
|
||||
u32 phy_rchng_cbcr;
|
||||
u32 pipediv2_cbcr;
|
||||
u8 _res6[0x131070 - 0x131064];
|
||||
struct clock_rcg phy_rchng_rcg;
|
||||
u8 _res7[0x131088 - 0x131078];
|
||||
u32 pipe_muxr;
|
||||
};
|
||||
|
||||
check_member(x1p42100_pcie, slv_q2a_axi_cbcr, 0x18);
|
||||
check_member(x1p42100_pcie, mstr_axi_cbcr, 0x28);
|
||||
check_member(x1p42100_pcie, cfg_ahb_cbcr, 0x34);
|
||||
check_member(x1p42100_pcie, phy_aux_cbcr, 0x44);
|
||||
check_member(x1p42100_pcie, pipe_cbcr, 0x50);
|
||||
check_member(x1p42100_pcie, phy_rchng_cbcr, 0x5c);
|
||||
check_member(x1p42100_pcie, phy_rchng_rcg, 0x70);
|
||||
check_member(x1p42100_pcie, pipe_muxr, 0x88);
|
||||
|
||||
struct x1p42100_gcc {
|
||||
struct x1p42100_gpll gpll0;
|
||||
u8 _res1[0x18004 - 0x0002c];
|
||||
u8 _res0[0x10004 - 0x0002c];
|
||||
struct x1p42100_pcie_noc pcie_noc;
|
||||
u8 _res1[0x18004 - 0x10054];
|
||||
|
||||
struct qupv3_clock qup_wrap1_s[8];
|
||||
u8 _res2[0x1e004 - 0x189c4];
|
||||
struct qupv3_clock qup_wrap2_s[8];
|
||||
|
|
@ -99,27 +189,33 @@ struct x1p42100_gcc {
|
|||
u32 qup_wrap2_core_2x_cbcr;
|
||||
u8 _res11[0x232c4 - 0x232bc];
|
||||
struct clock_rcg qup_wrap2_core_2x;
|
||||
u8 _res12[0x42004 - 0x232cc];
|
||||
u8 _res12[0x31000 - 0x232cc];
|
||||
struct x1p42100_pcie pcie_6a;
|
||||
u8 res13[0x42004-0x3108c];
|
||||
struct qupv3_clock qup_wrap0_s[8];
|
||||
u8 _res13[0x4b000 - 0x429c4];
|
||||
u8 _res14[0x4b000 - 0x429c4];
|
||||
u32 qspi_bcr;
|
||||
u32 qspi_cnoc_ahb_cbcr;
|
||||
u32 qspi_core_cbcr;
|
||||
struct clock_rcg qspi_core;
|
||||
u8 _res14[0x52000 - 0x4b014];
|
||||
u8 _res15[0x52000 - 0x4b014];
|
||||
u32 apcs_clk_br_en;
|
||||
u8 _res15[0x52008 - 0x52004];
|
||||
u8 _res16[0x52008 - 0x52004];
|
||||
u32 apcs_clk_br_en1;
|
||||
u8 _res16[0x52010 - 0x5200C];
|
||||
u8 _res17[0x52010 - 0x5200c];
|
||||
u32 apcs_clk_br_en2;
|
||||
u8 _res17[0x52018 - 0x52014];
|
||||
u8 _res18[0x52018 - 0x52014];
|
||||
u32 apcs_clk_br_en3;
|
||||
u8 _res18[0x52020 - 0x5201c];
|
||||
u8 _res19[0x52020 - 0x5201c];
|
||||
u32 apcs_clk_br_en4;
|
||||
u8 _res19[0x52028 - 0x52024];
|
||||
u8 _res20[0x52028 - 0x52024];
|
||||
u32 apcs_clk_br_en5;
|
||||
u8 _res20[0x52030 - 0x5202c];
|
||||
u8 _res21[0x52030 - 0x5202c];
|
||||
u32 apcs_pll_br_en;
|
||||
u8 _res22[0x8e000 - 0x52034];
|
||||
u32 pcie_6_phy_gdscr;
|
||||
u8 _res23[0xac01c - 0x8e004];
|
||||
u32 pcie_6a_phy_bcr;
|
||||
};
|
||||
|
||||
check_member(x1p42100_gcc, qup_wrap1_s, 0x18004);
|
||||
|
|
@ -142,6 +238,8 @@ check_member(x1p42100_gcc, apcs_clk_br_en3, 0x52018);
|
|||
check_member(x1p42100_gcc, apcs_clk_br_en4, 0x52020);
|
||||
check_member(x1p42100_gcc, apcs_clk_br_en5, 0x52028);
|
||||
check_member(x1p42100_gcc, apcs_pll_br_en, 0x52030);
|
||||
check_member(x1p42100_gcc, pcie_6_phy_gdscr, 0x8e000);
|
||||
check_member(x1p42100_gcc, pcie_6a_phy_bcr, 0xac01c);
|
||||
|
||||
enum clk_qup {
|
||||
QUP_WRAP0_S0,
|
||||
|
|
@ -170,11 +268,70 @@ enum clk_qup {
|
|||
QUP_WRAP2_S7,
|
||||
};
|
||||
|
||||
struct pcie {
|
||||
uint32_t *gdscr;
|
||||
uint32_t *clk;
|
||||
uint32_t *clk_br_en;
|
||||
int vote_bit;
|
||||
};
|
||||
|
||||
enum clk_gdsc {
|
||||
PCIE_6A_GDSC,
|
||||
PCIE_6_PHY_GDSC,
|
||||
MAX_GDSC
|
||||
};
|
||||
|
||||
enum clk_pcie_src_sel {
|
||||
PCIE_6A_PIPE_SRC_SEL = 0,
|
||||
PCIE_6A_XO_SRC_SEL = 2,
|
||||
};
|
||||
|
||||
enum clk_pcie {
|
||||
ANOC_PCIE_AT_CBCR = 1,
|
||||
ANOC_PCIE_QOSGEN_EXTREF_CBCR,
|
||||
DDRSS_PCIE_SF_QTB_CBCR,
|
||||
CNOC_PCIE_NORTH_SF_AXI_CBCR,
|
||||
CNOC_PCIE_SOUTH_SF_AXI_CBCR,
|
||||
NOC_PCIE_DCD_XO_CBCR,
|
||||
NOC_PCIE_SOUTH_DCD_XO_CBCR,
|
||||
NOC_PCIE_NORTH_DCD_XO_CBCR,
|
||||
CFG_NOC_PCIE_ANOC_AHB_CBCR,
|
||||
CFG_NOC_PCIE_ANOC_NORTH_AHB_CBCR,
|
||||
CFG_NOC_PCIE_ANOC_SOUTH_AHB_CBCR,
|
||||
AGGRE_NOC_PCIE_NORTH_AXI_CBCR,
|
||||
ANOC_PCIE_PWRCTL_CBCR,
|
||||
AGGRE_NOC_PCIE_SOUTH_AXI_CBCR,
|
||||
AGGRE_NOC_PCIE_HS_AXI_CBCR,
|
||||
AGGRE_NOC_PCIE_HS_NORTH_AXI_CBCR,
|
||||
AGGRE_NOC_PCIE_HS_SOUTH_AXI_CBCR,
|
||||
CNOC_PCIE_NORTH_SF_TUNNEL_AXI_CBCR,
|
||||
CNOC_PCIE_SOUTH_SF_TUNNEL_AXI_CBCR,
|
||||
PCIE_6A_SLV_Q2A_AXI_CLK,
|
||||
PCIE_6A_SLV_AXI_CLK,
|
||||
PCIE_6A_MSTR_AXI_CLK,
|
||||
PCIE_6A_CFG_AHB_CLK,
|
||||
PCIE_6A_AUX_CLK,
|
||||
PCIE_6A_PHY_AUX_CLK,
|
||||
PCIE_6A_PHY_RCHNG_CLK,
|
||||
PCIE_6A_PIPE_CLK,
|
||||
PCIE_6A_PIPEDIV2_CLK,
|
||||
PCIE_6A_PIPE_MUXR,
|
||||
PCIE_CLK_COUNT,
|
||||
};
|
||||
enum subsystem_reset {
|
||||
AOP_RESET_SHFT,
|
||||
CORE_SW_RESET,
|
||||
};
|
||||
|
||||
/* TODO: update as per datasheet */
|
||||
void clock_init(void);
|
||||
void clock_configure_qspi(uint32_t hz);
|
||||
void clock_enable_qup(int qup);
|
||||
void clock_configure_dfsr(int qup);
|
||||
void clock_configure_pcie(void);
|
||||
enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);
|
||||
enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
|
||||
enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
|
||||
|
||||
/* Subsystem Reset */
|
||||
static struct aoss *const aoss = (void *)AOSS_CC_BASE;
|
||||
|
|
|
|||
|
|
@ -1,11 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/addressmap.h>
|
||||
#include <soc/clock.h>
|
||||
#include <soc/qcom_qmp_phy.h>
|
||||
#include <soc/pcie.h>
|
||||
|
||||
/* Enable PIPE clock */
|
||||
int qcom_dw_pcie_enable_pipe_clock(void)
|
||||
{
|
||||
/* placeholder */
|
||||
/* Set pipe clock source */
|
||||
if (clock_configure_mux(PCIE_6A_PIPE_MUXR, PCIE_6A_PIPE_SRC_SEL)) {
|
||||
printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -13,9 +24,34 @@ int qcom_dw_pcie_enable_pipe_clock(void)
|
|||
/* Enable controller specific clocks */
|
||||
int32_t qcom_dw_pcie_enable_clock(void)
|
||||
{
|
||||
/* placeholder */
|
||||
int32_t ret, clk, gdsc;
|
||||
|
||||
return 0;
|
||||
/* Enable gdsc before enable pcie clocks */
|
||||
for (gdsc = PCIE_6A_GDSC; gdsc < MAX_GDSC; gdsc++) {
|
||||
ret = clock_enable_gdsc(gdsc);
|
||||
if (ret) {
|
||||
printk(BIOS_ERR, "Failed to enable gdsc\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure gcc_pcie*_phy_rchng_clk to 100mhz */
|
||||
clock_configure_pcie();
|
||||
|
||||
/* Enable pcie and PHY clocks */
|
||||
for (clk = ANOC_PCIE_AT_CBCR; clk < PCIE_CLK_COUNT; clk++) {
|
||||
if (clk == PCIE_6A_PIPE_MUXR) {
|
||||
printk(BIOS_DEBUG, "Skipping pipe\n");
|
||||
continue;
|
||||
}
|
||||
ret = clock_enable_pcie(clk);
|
||||
if (ret) {
|
||||
printk(BIOS_ERR, "Failed to enable %d clock\n", clk);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
write32(TCSR_GCC_PCIE_4L_CLKREF_EN_PCIE_ENABLE, 0x1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Turn on NVMe */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue