soc/qualcomm/x1p42100: Add CPU Clock boost support for X1P42100

Add support to increase the CPU clock frequency to 1.36(GHz).
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=Create an image.serial.bin and ensure it boots on X1P42100 and
CPU runs in 1.36GHz Frequency.

Change-Id: Ie51e032141bdfabf4c96b6891ec9f084561d97ff
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/qualcomm/x1p42100/clock.c

@@ -339,9 +339,55 @@ void clock_configure_pcie(void)
 			pcie_core_cfg, PCIE_PHY_RCHNG_FREQ, ARRAY_SIZE(pcie_core_cfg));
 }
 
+static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
+{
+	int ret;
+	struct alpha_pll_reg_val_config ncc0_pll_cfg = {0};
+
+	setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, (BIT(PLLSWCTL) | BIT(OVRCKMUXPLLFASTCLK)));
+
+	setbits64p(NCC0_NCC_CMU_NCC_PLL_CFG,
+		(((LOCKTMOUTCNT_VAL & LOCKTMOUTCNT_BMSK) << LOCKTMOUTCNT) |
+		((LOCKDEASSERTTMOUTCNT_VAL & LOCKDEASSERTTMOUTCNT_BMSK) << LOCKDEASSERTTMOUTCNT)));
+
+	ncc0_pll_cfg.reg_config_ctl = &ncc0->pll0_config_ctl;
+
+	ncc0_pll_cfg.config_ctl_val = (read32(ncc0_pll_cfg.reg_config_ctl) |
+					PFA_MSB_VAL << PFA_MSB |
+					RON_DEGEN_MULTIPLY_VAL << RON_DEGEN_MULTIPLY |
+					FBC_ALPHA_CAL_VAL << FBC_ALPHA_CAL |
+					PLL_COUNTER_ENABLE_VAL << PLL_COUNTER_ENABLE);
+
+	ncc0_pll_cfg.reg_config_ctl_hi = &ncc0->pll0_config_ctl_u;
+	ncc0_pll_cfg.config_ctl_hi_val = (read32(ncc0_pll_cfg.reg_config_ctl_hi) |
+					CHP_REF_CUR_TRIM_VAL << CHP_REF_CUR_TRIM |
+					ADC_KLSB_VALUE_VAL << ADC_KLSB_VALUE |
+					ADC_KMSB_VALUE_VAL << ADC_KMSB_VALUE);
+
+	ncc0_pll_cfg.reg_l = &ncc0->pll0_l;
+	ncc0_pll_cfg.l_val = l_val;
+
+	ncc0_pll_cfg.reg_alpha = &ncc0->pll0_alpha;
+	ncc0_pll_cfg.alpha_val = 0x00;
+
+	clock_configure_enable_gpll(&ncc0_pll_cfg, false, 0);
+
+	ncc0_pll_cfg.reg_mode = &ncc0->pll0_mode;
+	ncc0_pll_cfg.reg_opmode = &ncc0->pll0_opmode;
+	ret =  zondaole_pll_enable(&ncc0_pll_cfg);
+	if (ret != CB_SUCCESS)
+		return CB_ERR;
+
+	setbits64p(NCC0_NCC_CMU_NCC_CLK_CFG, BIT(SELCKMUXPLLFASTCLK));
+
+	return CB_SUCCESS;
+}
+
 static void speed_up_boot_cpu(void)
 {
-	/* Placeholder */
+	/* 1363.2 MHz */
+	if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz))
+		printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n");
 }
 
 void clock_init(void)

src/soc/qualcomm/x1p42100/include/soc/addressmap.h

@@ -9,6 +9,11 @@
 #define QSPI_BASE			0x088DC000
 #define TLMM_TILE_BASE			0x0F100000
 #define GCC_BASE			0x00100000
+#define NCC0_BASE			0x19A30000
+
+/* X1P42100 NCC0 PLL CONFIG ADDRESSES */
+#define NCC0_NCC_CMU_NCC_PLL_CFG	0x199A2010
+#define NCC0_NCC_CMU_NCC_CLK_CFG	0x199A2030
 
 /* X1P42100 QSPI GPIO PINS */
 #define QSPI_CS				GPIO(132)

src/soc/qualcomm/x1p42100/include/soc/clock.h

@@ -13,6 +13,9 @@
 #define GPLL0_MAIN_HZ		(600 * MHz)
 #define CLK_100MHZ		(100 * MHz)
 
+/* CPU PLL*/
+#define L_VAL_1363P2MHz		0x47
+
 #define PCIE_PHY_RCHNG_FREQ CLK_100MHZ
 
 #define QUPV3_WRAP0_CLK_ENA_S(idx)		(10 + idx)
@@ -22,6 +25,21 @@
 #define QUPV3_WRAP1_SE7_CLK_ENA			16
 #define QUPV3_WRAP2_SE7_CLK_ENA			17
 
+#define LOCKDEASSERTTMOUTCNT_BMSK		0xFFF
+#define LOCKTMOUTCNT_BMSK			0xFFFF
+
+#define LOCKDEASSERTTMOUTCNT_VAL		960LL
+#define LOCKTMOUTCNT_VAL			960LL
+
+#define PFA_MSB_VAL				2
+#define RON_DEGEN_MULTIPLY_VAL			1
+#define FBC_ALPHA_CAL_VAL			2
+#define PLL_COUNTER_ENABLE_VAL			1
+
+#define CHP_REF_CUR_TRIM_VAL			1
+#define ADC_KLSB_VALUE_VAL			4
+#define ADC_KMSB_VALUE_VAL			10
+
 enum clk_ctl_gpll_user_ctl_x1p42100 {
 	PLL_PLLOUT_MAIN_SHFT_X1P42100 = 0,
 	PLL_PLLOUT_EVEN_SHFT_X1P42100 = 1,
@@ -83,6 +101,30 @@ enum apcs_branch_en_vote {
 	NO_VOTE_BIT = -1,
 };
 
+enum ncc0_cmu_clk_cfg_x1p42100 {
+	OVRCKMUXPLLFASTCLK = 2,
+	SELCKMUXPLLFASTCLK = 3,
+	PLLSWCTL = 25,
+};
+
+enum ncc0_cmu_pll_cfg_x1p42100 {
+	LOCKTMOUTCNT = 0,
+	LOCKDEASSERTTMOUTCNT = 32,
+};
+
+enum ncc0_pll0_config_ctl {
+	PFA_MSB = 10,
+	RON_DEGEN_MULTIPLY = 18,
+	FBC_ALPHA_CAL = 20,
+	PLL_COUNTER_ENABLE = 27,
+};
+
+enum ncc0_pll0_config_ctl_u {
+	CHP_REF_CUR_TRIM = 0,
+	ADC_KLSB_VALUE = 13,
+	ADC_KMSB_VALUE = 23,
+};
+
 struct x1p42100_gpll {
 	u32 mode;
 	u32 opmode;
@@ -97,6 +139,22 @@ struct x1p42100_gpll {
 	u32 config_ctl_u1;
 };
 
+struct x1p42100_ncc0_clock {
+	u32 pll0_mode;
+	u32 pll0_l;
+	u32 pll0_alpha;
+	u32 pll0_user_ctl;
+	u32 pll0_user_ctl_u;
+	u32 pll0_config_ctl;
+	u32 pll0_config_ctl_u;
+	u32 pll0_config_ctl_u1;
+	u32 pll0_config_ctl_u2;
+	u32 pll0_test_ctl;
+	u32 pll0_test_ctl_u;
+	u32 pll0_test_ctl_u1;
+	u32 pll0_opmode;
+};
+
 struct x1p42100_pcie_noc {
 	u32 anoc_pcie_at_cbcr;
 	u32 anoc_pcie_tsctr_cbcr;
@@ -336,5 +394,5 @@ enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
 /* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;
 static struct x1p42100_gcc *const gcc = (void *)GCC_BASE;
-
+static struct x1p42100_ncc0_clock *const apss_ncc0 = (void *)NCC0_BASE;
 #endif	// __SOC_QUALCOMM_X1P42100_CLOCK_H__