soc/qualcomm/common: Update QUP register structure for QUP v3.2

The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.

Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/common/Kconfig

@@ -6,6 +6,12 @@ config SOC_QUALCOMM_COMMON
 	help
 	  Selected by platforms that use the common code.
 
+config QC_COMMON_QUPV3_2
+	bool
+	default n
+	help
+	  Selected by chipsets that has QUPv3 HW Version 2.
+
 if SOC_QUALCOMM_COMMON
 
 config QC_SDI_ENABLE

src/soc/qualcomm/common/clock.c

@@ -128,8 +128,15 @@ void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg,
 	unsigned int idx, s = qup % QUP_WRAP1_S0;
 	uint32_t reg_val;
 
-	qup_clk = qup < QUP_WRAP1_S0 ?
-				&gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+#if QUP_WRAP2_BASE
+	if (qup >= QUP_WRAP2_S0)
+		qup_clk = &gcc->qup_wrap2_s[s];
+	else
+#endif
+	if (qup >= QUP_WRAP1_S0)
+		qup_clk = &gcc->qup_wrap1_s[s];
+	else
+		qup_clk = &gcc->qup_wrap0_s[s];
 
 	clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr,
 			BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),

src/soc/qualcomm/common/include/soc/clock_common.h

@@ -45,6 +45,9 @@ struct clock_freq_config {
 
 struct qupv3_clock {
 	u32 cbcr;
+#if CONFIG(QC_COMMON_QUPV3_2)
+	u8 _res0[0x08];
+#endif
 	struct clock_rcg_mnd clk;
 	struct clock_rcg_dfsr dfsr_clk;
 };