soc/qualcomm/x1p42100: Add HS/SS PHY support for USB Type-C ports
Add HS/SS Phy for USB Type-C primary and secondary USB Type-C ports.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Boot from USB-C key on Google/Quenbi.
SS PHY used for Type-A and Type-C ports have different register layout.
[register address may vary for a similar register name]
USB4_USB3_EDP_DP_Con PHY Configuration - Type-C
USB3 Gen2 UNI PHY Configuration - Type-A
Hence it cannot be shared
Console logs:
[INFO ] Setting up USB HOST controller.
[DEBUG] USB HS PHY initialized for index 0
[DEBUG] USB HS PHY initialized for index 1
[DEBUG] QMP PHY MP0 init
[DEBUG] QMP PHY MP0 initialized and locked in 1674us
[DEBUG] QMP PHY MP1 init
[DEBUG] QMP PHY MP1 initialized and locked in 1674us
[DEBUG] USB HS PHY initialized for index 2
[DEBUG] QMP-1x16 USB4 DP PHY SS0 init
[DEBUG] QMP PHY SS0 initialized and locked in 1672us, phy_status: 0x86868686
[INFO ] Enabling SMB1 VBUS SuperSpeed
[DEBUG] SMB1 OTG Status: 0x00, State: 0x00
[ERROR] SMB1 OTG enable timeout after 100 ms, final state: 0x00
[ERROR] SMB1 OTG enable failed
[INFO ] SMB1 Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x3b
[INFO ] Src Status (0x2B08): 0x00
[INFO ] Mode Config (0x2B44): 0x00
[DEBUG] USB HS PHY initialized for index 3
[DEBUG] QMP-1x16 USB4 DP PHY SS1 init
[DEBUG] QMP PHY SS1 initialized and locked in 1672us, phy_status: 0x86868686
[INFO ] Enabling SMB2 VBUS SuperSpeed
[DEBUG] SMB2 OTG Status: 0x03, State: 0x03
[DEBUG] SMB2 OTG Status: 0x02, State: 0x02
[INFO ] SMB2 OTG block enabled successfully
[INFO ] SMB2 Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x49, VBUS Status (bit 5): 0
[INFO ] Src Status (0x2B08): 0x08
[INFO ] Mode Config (0x2B44): 0x00
[SPEW ] Configure USB in Host mode
[SPEW ] Configure USB Primary in Host mode
[SPEW ] Configure USB Secondary in Host mode
[INFO ] DWC3 and PHY setup finished
Change-Id: Icfec6f00ea41032e4fd17a5d99dea7529ef347fc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89372
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
45cedbb992