soc/qualcomm/common: Add clock reset function support

Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.

TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.


Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/common/clock.c

@@ -59,6 +59,15 @@ void clock_reset_bcr(void *bcr_addr, bool assert)
 		clrbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT));
 }
 
+/* Clock Reset Operations */
+void clock_reset(void *cbcr_addr, bool assert)
+{
+	if (assert)
+		setbits32(cbcr_addr, BIT(CLK_CTL_ARES_SHFT));
+	else
+		clrbits32(cbcr_addr, BIT(CLK_CTL_ARES_SHFT));
+}
+
 /* Clock GDSC Operations */
 enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr)
 {

src/soc/qualcomm/common/include/soc/clock_common.h

@@ -115,8 +115,10 @@ enum clk_ctl_cmd_rcgr {
 
 enum clk_ctl_cbcr {
 	CLK_CTL_EN_SHFT  = 0,
+	CLK_CTL_ARES_SHFT = 2,
 	CLK_CTL_OFF_SHFT = 31,
 	CLK_CTL_EN_BMSK = 0x1,
+	CLK_CTL_ARES_BMSK = 0x1 << CLK_CTL_ARES_SHFT,
 	CLK_CTL_OFF_BMSK = 0x80000000,
 };
 
@@ -148,6 +150,8 @@ enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr);
 
 void clock_reset_bcr(void *bcr_addr, bool assert);
 
+void clock_reset(void *cbcr_addr, bool assert);
+
 /*
  * clock_configure(): Configure the clock at the given clock speed (hz).  If hz
  * does not match any entries in the clk_cfg array, will throw and error and die().