Add the default configuration for fans as seen in the OS with
superiotool.
Change-Id: Iba142c2ad683962ee2c007f387e87adc77352dad
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add early EC space configuration as done in the vendor BIOS.
Change-Id: I058560733e3f5bb8c6df7d5401efad87911d3f4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Based on similar NCT6687D chip. Obtained the NCT6686D EC Space
Specification datasheet from Nuvoton via email request. Most of
the register definitions come from the EC Space Specification,
the rest has been figured out from MSI MS-7D25 BIOS.
Change-Id: I162f9d4067f0cba1d22d6cb5f98b68987719c038
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The R520G6SB server represents the next generation of the M50FCP2UR
Intel Server System, delivering cutting-edge performance and
versatility tailored for demanding data center and enterprise
workloads. Designed as a 2U dual-socket (2S) Birch Stream SP server
system, it integrates advanced features to meet demanding computing,
networking, and AI-driven application requirements.
Tested:
- USB: Front Panel 2 USB ports and 1 USB port on DCSCM
- PCIe: J1_MXIO_SLOT1 ~ J1_MXIO_SLOT5 (with PCIe SATA controller)
- M.2: M2_CN1, M2_CN2
- Mini Display Port
- Flash firmware from BMC's redfish interface (Out-of-band)
Build with Linux payload and Intel proprietary FSP.
Installed with dual Intel® Xeon® 6756E, one Micron 64GB DDR5
RDIMM 4800 and boots to Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I0590c82c9763bd07348bd86b134007ea4ed71d7a
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87574
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SC513G6 is a high-performance single-socket server motherboard
designed for AI, HPC, cloud, and data center applications.
Featuring Intel® Xeon® 6 Processors(LGA4710) support with up to
350W TDP, it delivers exceptional compute power, high-speed
networking, and versatile storage options in a compact SSI CEB
form factor.
Tested:
- USB: 4 USB ports
- PCIe: PCIE#1, PCIE#2, PCIE#3, PCIE#5 (with PCIe SATA controller,
and PCIE#4 is only available on CPU R1S SKU)
- M.2: M.2#1 and M.2#2
- LAN: 2 RJ45 GbE ports
- Graphic VGA Port
- - Flash firmware from BMC's redfish interface (Out-of-band)
Installed with Intel® Xeon® 6756E and boots to
Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I7b85e8548cfbdf9e52dc1956bd33e829020c052c
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add some simple execution time measurement code. It only logs execution
times if `DEBUG_RAM_SETUP` is selected. Note that this will fill things
like pre-RAM CBMEM console, but NRI's debug output is already extremely
verbose, and will become even more verbose as additional training steps
get added.
Future plans include measuring the time spent waiting for REUT hardware
to finish testing, as that is what takes most time for complex training
algorithms (which are yet to be published).
Tested on Asrock B85M Pro4, still boots to Arch Linux. Output example:
+------------------+------------+
| Task | msecs |
+------------------+------------+
| PROCSPD | 503 |
| INITMPLL | 33 |
| CONVTIM | 43 |
| CONFMC | 1 |
| MEMMAP | 39 |
| JEDECINIT | 1 |
| PRETRAIN | 23 |
| SOT | 394 |
| RCVET | 1448 |
| RDMPRT | 1088 |
| JWRL | 1975 |
| OPTCOMP | 0 |
| POSTTRAIN | 0 |
| ACTIVATE | 0 |
| SAVE_TRAIN | 0 |
| SAVE_NONT | 0 |
| RAMINITEND | 4 |
+------------------+------------+
| Total | 5558 |
+------------------+------------+
Note: the board had 4x dual-rank DIMMs installed, which gives the worst
possible boot time (more ranks to train, and that means more log output
to push through 115200 baud serial). Without debug logging, training is
substantially faster.
Change-Id: Ie4b6f6246e54f23d03babdb6fa0271538f69984e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TPM related default values for DRIVER_TPM_I2C_BUS and
TPM_TIS_ACPI_INTERRUPT based on schematic_1433518.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ifbd99265a36602b7d820cc088317579496144c9d
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I29070d871666f42615ba7afae9b9adb07e089fdc
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392 b:421064225
TEST=Run suspend_stress_test on moxie and verify that the device
suspends to S0ix.
Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/beechnutcity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: Ie115bd8e9044455185f82885a306849c509157bb
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87690
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/avenuecity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: I92589253915ad88bbb73736e10e7524b6be82499
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87689
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID
0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when
setting power limits due to the missing entry:
[ERROR] unknown SA ID: 0x4617, skipped power limits configuration
TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC.
Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add usb-a port3 setting to let funtion work fine.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I132f34a5c341f64d829bb78be9d400a77889f291
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87998
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add Elan touchscreen setting to let funtion work fine.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I7a6f56d46347f680f80feb691fc5104f8acf3f29
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88021
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Early init is only required for I2C2 since the DDI1 connector type
must be probed in romstage. The other I2C busses aren't used at the
moment and there's no need for early init.
TEST=Display init on amd/birman_plus still works. I2C0, I2C1 and I2C3
are initialized in ramstage after FSPS.
Change-Id: I0491d03464b675d18e42324580c91642aae4e727
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
In the factory setting, when a type-C charger is connected and the
battery is disconnected, it guarantees that the power limits are reduced
to avoid any unexpected shutdown or reset.
Change-Id: Ibe37c303149bbc253c5734664e8f17ee7005aca1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87959
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Adds a new assignment in variant_update_cpu_power_limits() to enforce
the desired PL4 power limit regardless of whether Fast VMode is enabled
or not.
Change-Id: I8b376d283b2a28333c8efc932bc2f776dfb5584a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87958
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new power limit configuration for Fast VMode in
Panther Lake SoC. The changes include the addition of a
`tdp_pl4_fastvmode` field to the `soc_power_limits_config` structure,
allowing distinct PL4 power limit values when Fast VMode is enabled.
The values come from document #813278 Panther Lake H Power Map Rev 1.6.
Change-Id: I971d1aa7dd22a8135272577712283b4565810799
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87954
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The definitions added are based on the following reference documents:
1. Document #815002 Panther Lake H External Design Specification
Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6
Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This variant of coreboot pairs with the brtk EC target.
This target enables development of the RTK EC on a Brox device.
BUG=b:421434445
TEST=cros build-packages --board brox coreboot
BRANCH=none
Change-Id: Ieaa3de6c30d0a0978506f23d927a4e96de71b16d
Signed-off-by: Bob Moragues <moragues@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87957
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
GCC 15 added a new `unterminated-string-initialization` warning. Even
though crossgcc is still using GCC 14, some Linux distributions (e.g.
Arch Linux) already started shipping GCC 15. Given that coreboot uses
`-Werror` (warnings are errors), this new warning causes build errors
for things built using the host toolchain, such as utilities. In this
case, cbfstool is affected, which prevents building coreboot images.
The nonstring attribute is used to tell the compiler whether or not a
string is intentionally not null terminated. Since the attribute is
only included in GCC 15 for multidimensional character arrays (and even
later for clang) we need to check the GCC version before using the
attribute.
On GCC version prior to GCC 15 the nonstring attribute will not be used,
but that is not a problem since the unterminated-string-initialization
warning only exists since GCC 15. So you can still build on all GCC
versions as before. This way it also works if your host toolchain is GCC
15 (which builds commonlib code for cbfstool) and your coreboot cross
toolchain is GCC 14 (which builds commonlib code for coreboot).
Clang is a diffent matter. According to the documentation, the nonstring
attribute only exists in version 21 which is not yet released by LLVM.
TEST=Build qemu/Q35 successfully
Change-Id: I919d71cb2811e91869ba1ff493a0719ddcc86c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87825
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality.
BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
the USB device.
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe8649297d3236a8896d1045cdf23cb4b1313e43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality. This
action requires setting the necessary register addresses, which is
handled by setup_usb_secondary_host().
BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
the USB device.
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I98534a833b344156a0e76e76ad7be88f98b2a967
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87977
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The GPIO which is used to determine whether the keyboard is connected
or not is dual-edge triggered, not level triggered, so adjust the
method name to reflect that. This ensures that the keyboard status
is updated on both connection and disconnection.
TEST=build/boot starlite_adl, verify tablet mode is correctly detected
when the keyboard is detached under both Windows and Linux.
Change-Id: I6c539fa264a2910589846e58d851acbe7c00900e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
PMC_GPP_F and GPP_F resolve to the same thing, but use the latter for
consistency and clarity. Non-functional change.
Change-Id: I005221cf7289ad2090b4231755d2eb4766bf67fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87992
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was masking the correct value set previously.
Change-Id: Ibe88fe4ad0de68b1188ec6a526497d5c0d75e56f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The option hooks are already set up at the SoC level, so
just add a new CFR form to expose the configuration.
Change-Id: I423e6b617ba60d7e44064ad9f4c3fec7e3e3fe75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use SoC common CFR forms where available.
Change-Id: I05106aca4402ec977a4593a4523dd7f30156b96c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The tri-state power-on-after-failure options don't make sense
for all boards, so add a CFR option which allows for a simple
toggle for powering on after power loss
Change-Id: I7624f16f74c46b7b487da00d0ff669ff4c187dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a new CFR form to configure ASPM on CPU-attached PCIe root ports,
with the correct default and range of values for the associated UPD.
Adjust the verbiage on the existing ASPM CFR form so that it is clear
that form is used to configure PCH-attached root ports.
Change-Id: I73dd98fc09bf095da15cf4beb2c282e4c91400cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since the default ASPM UPD value (and valid values) differ between CPU
and PCH-attached root ports, add a new option variable for CPU-attached
RPs so that they are not inadvertently set to an invalid value, leading
ASPM to be disabled on those RPs.
Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting
it will result in the CPU root port having ASPM disabled by FSP.
Fix this by modifying aspm_control_to_upd() to take into account
whether it's being called for a PCH RP or a CPU RP, and setting
the default value appropriately.
TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP
and downstream attached device have ASPM L1 enabled.
Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the recommendation at
https://review.coreboot.org/c/coreboot/+/84796/comment/21f615a2_99a41147/
and implement support for reading integer properties generically, using
their size to determine how much to read. This will be used for reading
`load`, `entry` and perhaps others.
Change-Id: I02d27eb5e23dfbfc1404d209ee8d60968e22bb80
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85643
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds the necessary infrastructure to support Realtek EC
controllers RTS5912/RTS5915 within the ChromeOS EC framework.
TEST=With this commit and 87702, flash to brox(rework realtek rts5915)
Boot normally and got those message from ap console:
[DEBUG] Google Chrome EC uptime: 698.137 seconds
[DEBUG] Google Chrome AP resets since EC boot: 6
[DEBUG] Google Chrome most recent AP reset causes:
[DEBUG] 635.380: 8 reset: during EC initialization
[DEBUG] 645.374: 32775 shutdown: entering G3
[DEBUG] 680.284: 8 reset: during EC initialization
[DEBUG] 684.586: 8 reset: during EC initialization
[DEBUG] Google Chrome EC reset flags at last EC boot: soft
[DEBUG] PNP: 0c09.0 init finished in 284 msecs
Change-Id: I44118c7b61a7efcee81acdd04be90b5022007a41
Signed-off-by: Jhan Bo Chao <jhan_bo_chao@realtek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87544
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the circuit schematic diagram, pujjocento uses GPP_E12
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E12 in gpio.h.
BUG=b:422656149
BRANCH=none
TEST=wp status update verified by toggling it on and off.
Change-Id: I91081f1b0ce5cb2fb3a29b96c1dcc18774f70f09
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
darp11 is an ArrowLake-H refresh of the previous model.
Change-Id: I1ac692a6591e0c7df89c5ba76a83764694145762
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Anx7625 reads EDID through AUX channel with I2C Over Aux operation,
reading 16-byte chunk a time. Sometimes, panel(CSOT MNB601LS1-3)
does not returns EDID raw data in time or returns OK without providing
data.
Root cause:
The measured difference between two adjacent UI signals of the AUX
signal is 36ns (518 - 482ns), it meets the VESA DP1.2/1.3 spec < 0.08UI
(48ns) requirement. However, this value exceeds the VESA DP1.1a spec
supported by the panel: max < 0.04UI (24ns) requirement, which exceeds
the tolerance value of the panel and leads to EDID communication
failure.
To address this issue, determined by tests, so that the issue did not
reproduce in over 200 tests
Test result:
Verified on 12pcs panels(8pcs issue panels, 4pcs new panels), 10pcs
tested 300 cycles, 2pcs tested 400 cycles, issue cannot be reproduced.
BUG=b:415946451
TEST=Tested on corsola over 200 times
BRANCH=corsola
Change-Id: I2d4f6b65b8f663ea9b9459e0343897a1223d631a
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enabling the mem_sub_sel and emi_n_sel MUXes in coreboot ensures proper
connectivity for multiple peripheral modules. Without these MUXes
enabled, some devices may experience communication failures or system
instability.
BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3ee0432ac1f102343e49a51008b3ea552b3f2857
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87974
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Nit-pick tidy up, for things like indentation and using true/false for bools.
Change-Id: Icae88494306b48695e69fd878e11e648327b443d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These boards only ever used one trackpad, so there is no need for this
to be set.
Change-Id: Ibabb663a83eea5f06c683cf2854ceed0487baf51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add DTT Power and Battery participants. These are used by DTT drivers to
more efficiently split power between SoC and dGPU and determine their
power limits.
Change-Id: I1e215366a79c0dd0f8a5d54c33fc718ba6b1302b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86820
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sumeet R.P. <sumeet4linux@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit refactors the Pantherlake SOC code by leveraging existing
P2SB device operations, thereby removing redundant definitions. The
change eliminates unnecessary device operation structures (pcd_p2sb_ops
and pcd_p2sb_2_ops) and replaces them with references to already defined
operations (p2sb_ops and p2sb2_ops). This is similar to how it is
handled in the Alder Lake codebase.
BUG=b:422284273
TEST=Boot on Fatcat with and without this commit, compare the logs, and
verify that the I/O memory resources for P2SB and P2SB2 devices are
accounted for and are identical.
Change-Id: I9304b6aa16f07fdc7d927cc2e27879db549ac774
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87955
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
