erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/brya/var/moxie: Enable RTD3 for SSD to resolve S0ix issue

Browse source 
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392 b:421064225
TEST=Run suspend_stress_test on moxie and verify that the device
suspends to S0ix.

Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
David Wu 2025-06-09 09:28:20 +08:00 • committed by Matt DeVillier
commit b322d30944
1 changed files with 7 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/mainboard/google/brya/variants/moxie/overridetree.cb
View file

@ -148,6 +148,13 @@ chip soc/intel/alderlake
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "srcclk_pin" = "0"
device generic 0 on end
end
end
device ref tbt_pcie_rp0 on
probe MB_USBC TC_USB4