mb/msi/{ms7d25,ms7e06}: Mimic the vendor BIOS early SIO init
Add early EC space configuration as done in the vendor BIOS. Change-Id: I058560733e3f5bb8c6df7d5401efad87911d3f4a Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Michał Żygowski
Matt DeVillier
parent
3c23d7b3a9
commit
a069c920f5
2 changed files with 111 additions and 44 deletions
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#include <device/pnp_ops.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6687d/nct6687d.h>
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#include <superio/nuvoton/nct6687d/nct6687d_ec.h>
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#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7)
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#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
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#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
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#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART)
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#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC)
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#define EC_IO_BASE 0xa20
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void bootblock_mainboard_early_init(void)
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{
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/* Replicate vendor settings for multi-function pins in global config LDN */
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nuvoton_pnp_enter_conf_state(SERIAL_DEV);
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pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
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pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
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nuvoton_pnp_enter_conf_state(GPIO_DEV);
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pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
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pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
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/* Below are multi-pin function */
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pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
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pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
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pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
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pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
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pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
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pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
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pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
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pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
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pnp_write_config(SERIAL_DEV, 0x24, 0x39);
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pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
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pnp_write_config(SERIAL_DEV, 0x26, 0x40);
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pnp_write_config(SERIAL_DEV, 0x27, 0x77);
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pnp_write_config(SERIAL_DEV, 0x28, 0x00);
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pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
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pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
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pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
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pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
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pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
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pnp_write_config(GPIO_DEV, 0x15, 0xaa);
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pnp_write_config(GPIO_DEV, 0x1a, 0x02);
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pnp_write_config(GPIO_DEV, 0x1b, 0x02);
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pnp_write_config(GPIO_DEV, 0x1d, 0x00);
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pnp_write_config(GPIO_DEV, 0x1e, 0xaa);
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pnp_write_config(GPIO_DEV, 0x1f, 0xb2);
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pnp_write_config(GPIO_DEV, 0x22, 0xbd);
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pnp_write_config(GPIO_DEV, 0x23, 0xdf);
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pnp_write_config(GPIO_DEV, 0x24, 0x39);
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pnp_write_config(GPIO_DEV, 0x25, 0xfe);
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pnp_write_config(GPIO_DEV, 0x26, 0x40);
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pnp_write_config(GPIO_DEV, 0x27, 0x77);
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pnp_write_config(GPIO_DEV, 0x28, 0x00);
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pnp_write_config(GPIO_DEV, 0x29, 0xfb);
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pnp_write_config(GPIO_DEV, 0x2a, 0x80);
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pnp_write_config(GPIO_DEV, 0x2b, 0x20);
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pnp_write_config(GPIO_DEV, 0x2c, 0x8a);
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pnp_write_config(GPIO_DEV, 0x2d, 0xaa);
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/* Set GPIO 06 as high output */
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pnp_write_config(GPIO_DEV, 0xF0, 0x00);
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pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40);
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pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00);
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pnp_set_logical_device(POWER_DEV);
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/* Configure pin for PECI */
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pnp_write_config(POWER_DEV, 0xf3, 0x80);
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nuvoton_pnp_exit_conf_state(POWER_DEV);
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/* Configure power fault detection */
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pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30);
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pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01);
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/* Configure yellow and green LED */
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pnp_write_config(POWER_DEV, 0xe7, 0x88);
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pnp_write_config(POWER_DEV, 0xe8, 0x07);
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pnp_set_logical_device(P80_UART_DEV);
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pnp_write_config(P80_UART_DEV, 0xe5, 0x0f);
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/* Configure EC */
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pnp_set_logical_device(EC_DEV);
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pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE);
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pnp_set_enable(EC_DEV, 1);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0);
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nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03);
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nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04);
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nuvoton_pnp_exit_conf_state(EC_DEV);
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if (CONFIG(CONSOLE_SERIAL))
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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@ -4,42 +4,76 @@
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#include <device/pnp_ops.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6687d/nct6687d.h>
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#include <superio/nuvoton/nct6687d/nct6687d_ec.h>
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#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7)
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#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
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#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
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#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART)
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#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC)
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#define EC_IO_BASE 0xa20
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void bootblock_mainboard_early_init(void)
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{
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/* Replicate vendor settings for multi-function pins in global config LDN */
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nuvoton_pnp_enter_conf_state(SERIAL_DEV);
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pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
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pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
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nuvoton_pnp_enter_conf_state(GPIO_DEV);
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pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
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pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
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/* Below are multi-pin function */
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pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
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pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
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pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
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pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
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pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
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pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
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pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
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pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
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pnp_write_config(SERIAL_DEV, 0x24, 0x39);
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pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
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pnp_write_config(SERIAL_DEV, 0x26, 0x40);
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pnp_write_config(SERIAL_DEV, 0x27, 0x77);
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pnp_write_config(SERIAL_DEV, 0x28, 0x00);
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pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
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pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
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pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
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pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
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pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
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pnp_write_config(GPIO_DEV, 0x15, 0xaa);
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pnp_write_config(GPIO_DEV, 0x1a, 0x02);
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pnp_write_config(GPIO_DEV, 0x1b, 0x02);
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pnp_write_config(GPIO_DEV, 0x1d, 0x00);
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pnp_write_config(GPIO_DEV, 0x1e, 0xaa);
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pnp_write_config(GPIO_DEV, 0x1f, 0xb2);
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pnp_write_config(GPIO_DEV, 0x22, 0xbd);
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pnp_write_config(GPIO_DEV, 0x23, 0xdf);
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pnp_write_config(GPIO_DEV, 0x24, 0x39);
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pnp_write_config(GPIO_DEV, 0x25, 0xfe);
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pnp_write_config(GPIO_DEV, 0x26, 0x40);
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pnp_write_config(GPIO_DEV, 0x27, 0x77);
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pnp_write_config(GPIO_DEV, 0x28, 0x00);
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pnp_write_config(GPIO_DEV, 0x29, 0xfb);
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pnp_write_config(GPIO_DEV, 0x2a, 0x80);
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pnp_write_config(GPIO_DEV, 0x2b, 0x20);
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pnp_write_config(GPIO_DEV, 0x2c, 0x8a);
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pnp_write_config(GPIO_DEV, 0x2d, 0xaa);
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/* Set GPIO 06 as high output */
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pnp_write_config(GPIO_DEV, 0xF0, 0x00);
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pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40);
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pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00);
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pnp_set_logical_device(POWER_DEV);
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/* Configure pin for PECI */
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pnp_write_config(POWER_DEV, 0xf3, 0x80);
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nuvoton_pnp_exit_conf_state(POWER_DEV);
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/* Configure power fault detection */
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pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30);
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pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01);
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/* Configure yellow and green LED */
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pnp_write_config(POWER_DEV, 0xe7, 0x88);
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pnp_write_config(POWER_DEV, 0xe8, 0x07);
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pnp_set_logical_device(P80_UART_DEV);
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pnp_write_config(P80_UART_DEV, 0xe5, 0x0f);
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/* Configure EC */
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pnp_set_logical_device(EC_DEV);
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pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE);
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pnp_set_enable(EC_DEV, 1);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0);
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nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03);
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nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01);
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nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04);
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nuvoton_pnp_exit_conf_state(EC_DEV);
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if (CONFIG(CONSOLE_SERIAL))
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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