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mb/google/fatcat/fmap: Add 1 MB from SI_BIOS to SI_All

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This patch updates the flash layout for the fatcat variants. The changes
are as follows,

SI_ALL:      8MB --> 9MB
SI_BIOS:     24MB --> 23MB
  FW_A/B:    7.5MB --> 8.5MB
  RW_UNUSED: 2MB --> 0MB

BUG=b:419831198
TEST=Able to build and boot google/fatcat

Change-Id: I615b26ccdbbf3cfcc18dfb5917e13f0700ba673c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Pranava Y N 2025-05-27 15:28:47 +05:30 • committed by Subrata Banik
commit 5fcbc709ec
1 changed files with 17 additions and 17 deletions
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34
src/mainboard/google/fatcat/chromeos.fmd
View file

@ -1,23 +1,9 @@
FLASH 32M {
SI_ALL 8M {
SI_ALL 9M {
SI_DESC 16K
SI_ME
}
SI_BIOS 24M {
RW_SECTION_A 8M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
# This section starts at the 16M boundary in SPI flash.
# PTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 8M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
}
SI_BIOS 23M {
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
@ -31,8 +17,22 @@ FLASH 32M {
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
RW_SECTION_A 8704K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
# FIXME: b/419831198
# This section starts at the 16M boundary in SPI flash.
# PTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 8704K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
}
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {