mb/starlabs/byte: Use SoC common CFR forms

Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED
to keep existing behavior.

Change-Id: I5aa0d6e5a59a1f4a1fdc379d2eaf13f7acb6fa91
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87983
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2025-05-02 13:24:08 -05:00 committed by Sean Rhodes
commit 3f16609ba2
2 changed files with 3 additions and 71 deletions

View file

@ -2,6 +2,7 @@ config BOARD_STARLABS_BYTE_SERIES
def_bool n
select BOARD_ROMSIZE_KB_16384
select CRB_TPM
select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
select DRIVERS_EFI_VARIABLE_STORE
select DRIVERS_INTEL_PMC
select DRIVERS_OPTION_CFR_ENABLED

View file

@ -1,13 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <boot/coreboot_tables.h>
#include <commonlib/coreboot_tables.h>
#include <console/cfr.h>
#include <drivers/option/cfr_frontend.h>
#include <inttypes.h>
#include <intelblocks/pcie_rp.h>
#include <string.h>
#include <types.h>
#include <intelblocks/cfr.h>
#include <variants.h>
static const struct sm_object gna = SM_DECLARE_BOOL({
@ -17,31 +13,6 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
.default_value = false,
});
static const struct sm_object me_state = SM_DECLARE_ENUM({
.opt_name = "me_state",
.ui_name = "Intel Management Engine",
.ui_helptext = "Enable or disable the Intel Management Engine",
.default_value = 1,
.values = (const struct sm_enum_value[]) {
{ "Disabled", 1 },
{ "Enabled", 0 },
SM_ENUM_VALUE_END },
});
static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
.opt_name = "me_state_counter",
.ui_name = "ME State Counter",
.flags = CFR_OPTFLAG_SUPPRESS,
.default_value = 0,
});
static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
.opt_name = "power_on_after_fail",
.ui_name = "Power on after failure",
.ui_helptext = "Automatically turn on after a power failure",
.default_value = false,
});
static const struct sm_object power_profile = SM_DECLARE_ENUM({
.opt_name = "power_profile",
.ui_name = "Power Profile",
@ -54,46 +25,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
.opt_name = "pciexp_aspm",
.ui_name = "PCI ASPM",
.ui_helptext = "Controls the Active State Power Management for PCI devices."
" Enabling this feature can reduce power consumption of"
" PCI-connected devices during idle times.",
.default_value = ASPM_L0S_L1,
.values = (const struct sm_enum_value[]) {
{ "Disabled", ASPM_DISABLE },
{ "L0s", ASPM_L0S },
{ "L1", ASPM_L1 },
{ "L0sL1", ASPM_L0S_L1 },
SM_ENUM_VALUE_END },
});
static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
.opt_name = "pciexp_clk_pm",
.ui_name = "PCI Clock Power Management",
.ui_helptext = "Enables or disables power management for the PCI clock. When"
" enabled, it reduces power consumption during idle states."
" This can help lower overall energy use but may impact"
" performance in power-sensitive tasks.",
.default_value = true,
});
static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
.opt_name = "pciexp_l1ss",
.ui_name = "PCI L1 Substates",
.ui_helptext = "Controls deeper power-saving states for PCI devices."
" Enabling this feature allows supported devices to achieve"
" lower power states at the cost of slightly increased"
" latency when exiting these states.",
.default_value = L1_SS_L1_2,
.values = (const struct sm_enum_value[]) {
{ "Disabled", L1_SS_DISABLED },
{ "L1.1", L1_SS_L1_1 },
{ "L1.2", L1_SS_L1_2 },
SM_ENUM_VALUE_END },
});
static const struct sm_object vtd = SM_DECLARE_BOOL({
.opt_name = "vtd",
.ui_name = "VT-d",
@ -131,7 +62,7 @@ static struct sm_obj_form processor = {
static struct sm_obj_form power = {
.ui_name = "Power",
.obj_list = (const struct sm_object *[]) {
&power_on_after_fail,
&power_on_after_fail_bool,
NULL
},
};