mb/starlabs/byte: Use SoC common CFR forms
Use SoC common CFR forms; select CSE_DEFAULT_OPTION_STATE_DISABLED to keep existing behavior. Change-Id: I5aa0d6e5a59a1f4a1fdc379d2eaf13f7acb6fa91 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87983 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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2 changed files with 3 additions and 71 deletions
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@ -2,6 +2,7 @@ config BOARD_STARLABS_BYTE_SERIES
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select CRB_TPM
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select CSE_DEFAULT_CFR_OPTION_STATE_DISABLED
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select DRIVERS_EFI_VARIABLE_STORE
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select DRIVERS_INTEL_PMC
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select DRIVERS_OPTION_CFR_ENABLED
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@ -1,13 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boot/coreboot_tables.h>
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#include <commonlib/coreboot_tables.h>
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#include <console/cfr.h>
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#include <drivers/option/cfr_frontend.h>
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#include <inttypes.h>
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#include <intelblocks/pcie_rp.h>
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#include <string.h>
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#include <types.h>
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#include <intelblocks/cfr.h>
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#include <variants.h>
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static const struct sm_object gna = SM_DECLARE_BOOL({
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@ -17,31 +13,6 @@ static const struct sm_object gna = SM_DECLARE_BOOL({
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.default_value = false,
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});
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static const struct sm_object me_state = SM_DECLARE_ENUM({
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.opt_name = "me_state",
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.ui_name = "Intel Management Engine",
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.ui_helptext = "Enable or disable the Intel Management Engine",
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.default_value = 1,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", 1 },
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{ "Enabled", 0 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
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.opt_name = "me_state_counter",
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.ui_name = "ME State Counter",
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.flags = CFR_OPTFLAG_SUPPRESS,
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.default_value = 0,
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});
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static const struct sm_object power_on_after_fail = SM_DECLARE_BOOL({
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.opt_name = "power_on_after_fail",
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.ui_name = "Power on after failure",
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.ui_helptext = "Automatically turn on after a power failure",
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.default_value = false,
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});
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static const struct sm_object power_profile = SM_DECLARE_ENUM({
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.opt_name = "power_profile",
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.ui_name = "Power Profile",
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@ -54,46 +25,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
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.opt_name = "pciexp_aspm",
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.ui_name = "PCI ASPM",
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.ui_helptext = "Controls the Active State Power Management for PCI devices."
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" Enabling this feature can reduce power consumption of"
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" PCI-connected devices during idle times.",
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.default_value = ASPM_L0S_L1,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", ASPM_DISABLE },
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{ "L0s", ASPM_L0S },
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{ "L1", ASPM_L1 },
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{ "L0sL1", ASPM_L0S_L1 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
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.opt_name = "pciexp_clk_pm",
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.ui_name = "PCI Clock Power Management",
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.ui_helptext = "Enables or disables power management for the PCI clock. When"
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" enabled, it reduces power consumption during idle states."
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" This can help lower overall energy use but may impact"
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" performance in power-sensitive tasks.",
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.default_value = true,
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});
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static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
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.opt_name = "pciexp_l1ss",
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.ui_name = "PCI L1 Substates",
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.ui_helptext = "Controls deeper power-saving states for PCI devices."
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" Enabling this feature allows supported devices to achieve"
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" lower power states at the cost of slightly increased"
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" latency when exiting these states.",
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.default_value = L1_SS_L1_2,
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.values = (const struct sm_enum_value[]) {
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{ "Disabled", L1_SS_DISABLED },
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{ "L1.1", L1_SS_L1_1 },
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{ "L1.2", L1_SS_L1_2 },
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SM_ENUM_VALUE_END },
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});
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static const struct sm_object vtd = SM_DECLARE_BOOL({
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.opt_name = "vtd",
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.ui_name = "VT-d",
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@ -131,7 +62,7 @@ static struct sm_obj_form processor = {
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static struct sm_obj_form power = {
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.ui_name = "Power",
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.obj_list = (const struct sm_object *[]) {
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&power_on_after_fail,
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&power_on_after_fail_bool,
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NULL
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},
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};
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