Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.
Test on the StarLite Mk III and Mk IV:
Without VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 88
With VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 102
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a loader that will load the IBB into the CSE via the Ring Protocol
Buffer.
All registers were taken from Intel document number #336561.
Change-Id: Ia41e3909f8099d2ea864166e9ea03e10e40a1b68
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot's method of creating IFWI is to modify an existing IFWI
images by deleting the IBB, replacing the IBBL with the bootblock
and everything else is put in the OBB.
This poses a problem when using Intel's FIT or technologies such
as Boot Guard. The main problem is that the IBB is never verified by
the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP
and stays in recovery mode. The vast majority of the stages in
Apollolake's Secure Boot flow is not met using this method (Intel
document number 597827 summarizes these steps).
This patch series is based on the principles of a patch from Brenton
Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the
correct functions to complete the Secure Boot flow. This is to copy
the IBB from SRAM using the CSE's Ring Buffer Protocol.
These binaries can then be used by FIT or coreboot's existing
method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is
the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb"
must be recreated.
Whilst this option doesn't form a complete image, the components it
builds will work as Intel intended them to once stitched correctly into
an IFWI image.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This configures FSP UPDs for PCH PM minimum assertion widths and
reset power cycle duration per mainboard variants configuration.
This also checks the reset power cycle duration is not be smaller
than SLP_S3, SLP_S4 and SLP_A Minimum Assertion Width.
PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
The Reset Power Cycle Duration starts at 20ms and increases by 20ms
for each step, beginning from 0x0 to 0xFF. Each subsequent increment
corresponds to an additional 20 milliseconds in duration.
Reference:
Panther Lake External Design Specification (EDS) Volume 2 (#813032)
BUG=None
TEST=Build a fatcat coreboot and boot to OS without an issue.
Change-Id: I7234c7539c1e7eb5e2b8c04ccff6c62c853d6807
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88443
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces a new configuration option
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` that allows users to
specify if their mainboard is using Panther Lake pre-production silicon
aka Engineering Silicon (ES) with pre-production signed ME Firmwares.
The default value is set to 'n', ensuring it is disabled unless
explicitly chosen.
BUG=b:424355826
TEST=No change in the functionality, just added new configs.
Change-Id: I8ad83b07f057a227b62e33b6c6c0f46c3952be6b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88218
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces Direct Memory Access (DMA) support for the Intel
Fast SPI block, enhancing data transfer capabilities from SPI flash
memory. The primary motivation for this addition is to improve
performance in multitasking environments by offloading read operations
to DMA, thus freeing up CPU resources for other tasks. The traditional
memory-mapped SPI flash read operations can be CPU-intensive and slow in
scenarios where large data volumes are transferred.
This feature is gated by a FAST_SPI_DMA configuration option. The DMA
operations are integrated with existing SPI flash read functionalities,
ensuring fallback to memory-mapped operations if DMA is unsupported or
fails. The DMA code implementation uses mutex-based synchronization to
ensure thread-safe DMA transactions.
The boot_device_ro() function has been modified to check for DMA support
and installs custom DMA operations when available.
We conducted measurements on a 200 KB data transfer and noticed a 1.8%
improvement with DMA compared to memcpy on memory-mapped SPINOR, with
DMA taking 10.8 ms and memcpy taking 11 ms.
Change-Id: I4b4ca9ff08e436ca627afa6b0d9bb00f3c450a5e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88277
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the memory layout for AP Firmware boot on the
Qualcomm x1p42100 SoC. This update is crucial to ensure that all
processors and co-processors can successfully load their
respective blobs during the process of booting to the OS.
TEST=Successfully booted google/blueu.
Change-Id: Ibce385e9d201f0a3c5daf19e8dfe235fa9f695af
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The boot time is improved by 50ms in bootblock.
BUG=b:379008996
BRANCH=none
TEST=check the boot time by `cbmem`.
(previous)
11:start of bootblock 247,551 (60)
12:end of bootblock 312,495 (64,944)
(now)
11:start of bootblock 255,424 (60)
12:end of bootblock 270,911 (15,487)
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I0c3a5cff7eecb67e34d8ff1d3084f6a34d9cdbe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88368
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The Boot Profile for use with the IFWI Boot Flow. The selected profile
should be equal to or higher than the one configured in IFWI.
No Profile
Since its inception, coreboot has ignored the Boot Flow designed by
Intel; this only uses an IBB and OBB. Neither are measured or verified
and mapped without assistance.
Legacy
Profile 0 is for platforms that do not wish to enable Boot Guard boot
block verification or measurement enforcement.
Verified
Profile 1 is strict Verification enforcement. It prevents unverified
BIOS components from running.
Verified and Measured
Boot Guard Profile 2 is strict Verification and Measurement
enforcement; this prevents unverified BIOS components from running.
Upon manufacturing completion, this value is burned into an FPF
and is permanent. This setting is only configurable when OEM signing
is enabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83d2fd134e1a893766f625fe2e2ddd81d48f9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SPI NOR clock from 26MHz to 52MHz to improve boot time.
BUG=b:379008996
BRANCH=none
TEST=Verified clock rate via oscilloscope, and measure boot time with
cbmem
(previous) Total Time: 800,539
(now) Total Time: 739,292
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe3df8200417fa9a8292bfd3c29339b7d125e3c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
There can be cases where it is needed to provide the SPD data in a
different way than an EEPROM or CBFS file. This patch adds a third
method where the SPD data can be provided in a memory buffer for
memory-down configurations. Where this memory buffer comes from
and how SPD data is filled in is up to the mainboard code.
To use this new method set 'spd_data.in_mem' to 'true' and provide a
pointer to the SPD data in memory via 'spd_data.ptr' where
'spd_data.len' holds the length of the SPD data in that buffer.
This feature is useful for Siemens mainboards where the SPD data is part
of a larger configuration block called 'HWInfo block'. Though this block
itself do reside in CBFS, the SPD data cannot simply be indexed into
(like with the cbfs_index). Instead, the hwinfo-lib is used to get
dedicated fields from that block, this includes the SPD data, too. With
this patch the SPD data can be retrieved from HWInfo block and passed as
a buffer to the memory initialization code.
Change-Id: I2bd4970967cfe81bba96d8e2b2fd3a0bb85430c4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88258
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the platform reporting logic to recognize the
Wildcat Lake SoC CPU ID.
Key changes:
- Add CPUID_WILDCATLAKE_A0 to the list of recognized CPU IDs in
the platform reporting module.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I8c9e81446a12ee0a6e18f1ba3f36166652a05f5e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88271
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Add parameters and default setting of FSP
BUG=b:407645233
TEST= IOMT verification confirmed, that USB settings can be updated through FSP parameters.
Change-Id: Idbd9ee795b74f43921472ef42a95b2be23af6f5d
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Extract code for disabling secure mode from mtk_ddp_init and implement
it as mtk_display_disable_secure_mode(). This allows disabling display
secure mode without using DDP, for example, when FW display is not
needed.
Unlike previous SoCs, MT8189 is designed so that access to display
registers defaults to secure mode, due to specific product requirements.
However, Chromebook products do not use this setting and instead require
the register permissions to be set for normal mode access, consistent
with previous SoC behavior.
Also reordered function declarations to group similar types (e.g.,
display, DDP) together for better readability.
BUG=b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ic378ef62540c408ccd59e482abfe9f9c8ca5a13d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify
XO Source clock frequency value to 19.2KHz. The register
details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100
Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.
Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load PI image through CBFS and pass parameters of PI image to mtk_fsp
for parsing.
BUG=b:379008996
BRANCH=none
TEST=check the boot log:
[INFO ] CBFS: Found 'pi_img.img' @0x3d880 size 0x10b in mcache @0xfffdd314
[DEBUG] mtk_init_mcu: Loaded (and reset) pi_img.img in 14 msecs (720 bytes)
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iada90ad4298d0a91ad73798252db19b12f2f6ef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88266
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, move PI image related code to
common folder. The function add_pi_image_params is renamed to
pi_image_add_mtk_fsp_params for prefix consistency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If5e3d9e6d5f97ead763ef9adc2d23bce0ed68877
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88265
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit enables `ARM64_USE_ARM_TRUSTED_FIRMWARE` for the
Qualcomm X1P42100 SoC.
Selecting this option ensures that coreboot is configured to
integrate with ARM Trusted Firmware (TF-A), which is essential
for proper boot and power management functionality on this platform.
BUG=b:424149462
TEST=Able to build google/bluey.
Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
MT8189 is equipped with the Power Mode Resource Collector (PMRC)
feature, and the implementation to set PMIF to normal mode is the same
as in pmif_spmi_v2. Use pmif_spmi_v2 to correct the configuration to
allow PMIF to properly enter normal mode on MT8189.
BUG=b:379008996
BRANCH=none
TEST=check the following logs for PMIC communication
[DEBUG] pmic_efuse_setting: Set efuses in 10 msecs
[INFO ] [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_boot,330: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_enable_dcxo,66: con=0x486, osc32con=0xfe69, sec=0x0
[INFO ] [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
[INFO ] [RTC]rtc_osc_init,62: osc32con val = 0xfe69
[INFO ] [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88244
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This reverts commit 2e495b09d5.
Reason for revert: mmio_tseg is reserved twice in
mc_add_dram_resources, where the duplication is introduced by
commit 43b0ed7089 ("soc/intel/xeon_sp: Improve final MTRR solution")
Change-Id: I0f1bf757d8d1fc449e4efc0ec171c6f982f79e9e
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from
old SoCs with dptx_v1. The formulas for register calculation are
different:
- The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp
on MT8196, while on older SoCs it is hsync + hbp.
- The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp
on MT8196, but vsync + vbp on earlier SoCs.
The current formula for MT8196 only works correctly when ha/va are
multiples of 4 and hfp/vfp are 0. The new formula fixes display errors
at resolutions like 1366x768 (ha=1366, hfp=48).
To distinguish these differences, an edp_version parameter is added.
Also update the following settings for correct configuration:
- Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous
incorrect setting.
- Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple
of 4 (such as 1366).
BUG=b:400886838
BRANCH=rauru
TEST=Check the display function on Navi
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Based on the dptx_v2 common driver, add eDP driver to adjust training
flow and turn off PHY power before PHY configuration to prevent
potential link training failures. Also correct the DISP_DVO0 address
since the initial value is not thoroughly checked during early bring-up.
DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI
or simply digital video output. DISP represents "display", while DVO is
the abbreviation of "digital video output". This version of DISP_DVO is
mainly designed for eDP1.5 protocol.
BUG=b:400886838,b:422095960
BRANCH=none
TEST=Check the display function on Skywalker. Check the log for
"EQ training pass".
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I59cfdae1d13cf7fb9627a4d534602cb309df3d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88168
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the eMMC specification, the maximum allowed source clock
frequency is 200MHz. Currently, a 416MHz source clock is used, which
after division results in 208MHz. This exceeds the spec limit.
Additionally, considering possible frequency fluctuations and desense
issues, 384MHz is a more reasonable and safer value. Limit the source
clock frequency to 384MHz to ensure compliance with the eMMC
specification and improve system stability.
BUG=b:396258620
BRANCH=none
TEST=echo fmeter > /proc/clkdbg ; cat /proc/clkdbg |grep msdcpll
30: fm_msdcpll_ck : 383500
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3c704b1200dd89a05476a5b14b75950aead51f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently, the overcurrent pin enum is only defined up to OC5. However,
PCH-H chips support up to OC7 according to the 100 and 200 Series PCH
datasheets [1][2].
[1] Intel document 332690
[2] Intel document 335192
Change-Id: Ie35612eeaed2196caccc514429c7d80f84cf09a8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88159
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 32ebaef73c
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.
PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.
The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.
Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.
Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).
BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.
It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.
The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.
TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
device operating an H12Xe Panther Lake SoC.
Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.
It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.
This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.
TEST=Successfully compile the Fatcat board target.
Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).
TEST=Invoke the following set of acpidbg commands to verify that the
_RST method still reaches state 2.
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2
Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Introduce a new ACPI field, "WFDL", to specify the Power Level Device
Reset (PLDR) delay for Wi-Fi operations. This replaces the previously
hardcoded delay value, allowing for easier adjustment and configuration
of the PLDR timing in the future. By utilizing a named field, this
change facilitates potential updates to delay configurations.
Change-Id: I0f243ccf404afb83554136a3a310a98d6100d8ff
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Align the ACPI code comments with the actual generated code for Wi-Fi
power resource management. This change enhances the maintainability and
readability of the code by ensuring that comments accurately reflect the
runtime SSDT code.
Change-Id: Ie33c716305251356a462b086fa8c61ec8d16c3cb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88112
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The change introduces new Advanced Configuration and Power Interface
(ACPI) methods to handle Bluetooth device states, including status
checks and device reset procedures. Specifically, it adds a Power
Resource for Reset (_PRR) method and the associated power resources to
enable Operating System (OS)-level resets for Connectivity Integrated
(CNVi) Bluetooth devices as specified in Intel document
number 559910. This allows the OS to perform Bluetooth hardware recovery
in case of errors, ensuring compliance with Intel's standards. The Power
Resource ACPI code was adapted from Panther Lake (PTL) Firmware Support
Package (FSP) revision 3144.01.
The new ACPI Bluetooth code introduces the CNMT mutex, similar to the
USB Bluetooth ACPI code, to avoid simultaneous CNVi resets when
executing Wi-Fi and Bluetooth power resource _RST methods.
TEST=The following two use cases were verified using acpidbg on a Fatcat
device.
1. Test CNVi Bluetooth _RST() completion.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVB.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVB.RSTT 1' # 0x1
acpidbg -b 'evaluate \_SB.PCI0.CNVB.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x2
2. Test that CNVi Wi-Fi _RST calls CNVi Bluetooth CFLR method.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x1
Change-Id: I2389901faf4fad131bb7226e356b47f4b1a4ddac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Qualcomm's latest SoC, the x1p42100, lacks upstreamed blobs. This
prevents coreboot builds because the default setting marks
CONFIG_USE_QC_BLOBS=y. As a result, build errors occur when the new
Qualcomm SoC blobs aren't in the upstream.
This change introduces `QC_BLOBS_UPSTREAM` Kconfig and set to default
`N` to build QC platform without relying on upstream blob support.
This is necessary for bringing up a new QC SoC-based platform, as
public QC blobs won't be available until later in the year. This
ensures that early QC development can proceed for QC SoC based
without depending on upstream blobs.
Override this Kconfig when QC blobs are available in upstream for
latest X1P42100 SoC.
TEST=Able to build google/bluey.
Change-Id: I04fde6e8917fb3f88c58eb2b55b47de1c2d33518
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit adds horizontal alignment support for splash screen
logos into the existing helper function `calculate_logo_coordinates()`.
Updated helper function determines the X-coordinate for
logo placement based on specified horizontal alignment (left, right,
or center).
The `soc_load_logo_by_coreboot()` function is updated to utilize this
helper for footer logo placement when the panel orientation is
rotated (`LB_FB_ORIENTATION_RIGHT_UP`, `LB_FB_ORIENTATION_LEFT_UP`,
or `LB_FB_ORIENTATION_BOTTOM_UP`).
A new enum, `fw_splash_horizontal_alignment`, is defined in
`intelblocks/cfg.h` to explicitly represent these horizontal alignment
options, complete with descriptive comments and ASCII art.
This enhancement provides greater flexibility in positioning splash
screen elements, especially useful for rotated displays (for the footer
firmware splash screen).
BUG=b:423591644
TEST=Able to rotate the firmware splash screen (including footer logo)
while using portrait panel.
Change-Id: I23ae6d06e1df9cad1b2907a5c02b619dc831d468
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88030
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
