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soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz

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Set SPI NOR clock from 26MHz to 52MHz to improve boot time.

BUG=b:379008996
BRANCH=none
TEST=Verified clock rate via oscilloscope, and measure boot time with
cbmem
(previous) Total Time: 800,539
(now) Total Time: 739,292

Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ibe3df8200417fa9a8292bfd3c29339b7d125e3c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Vince Liu 2025-06-25 08:48:12 +08:00 • committed by Yu-Ping Wu
commit f323adb19f
1 changed files with 1 additions and 1 deletions
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2
src/soc/mediatek/mt8189/pll.c
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@ -261,7 +261,7 @@ static const struct mux_sel mux_sels[] = {
{ .id = CLK_TOP_DP_SEL, .sel = 4 },
{ .id = CLK_TOP_EDP_SEL, .sel = 4 },
{ .id = CLK_TOP_EDP_FAVT_SEL, .sel = 4 },
{ .id = CLK_TOP_SFLASH_SEL, .sel = 0 },
{ .id = CLK_TOP_SFLASH_SEL, .sel = 2 },
{ .id = CLK_TOP_ECC_SEL, .sel = 5 },
};