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soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189

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MT8189 is equipped with the Power Mode Resource Collector (PMRC)
feature, and the implementation to set PMIF to normal mode is the same
as in pmif_spmi_v2. Use pmif_spmi_v2 to correct the configuration to
allow PMIF to properly enter normal mode on MT8189.

BUG=b:379008996
BRANCH=none
TEST=check the following logs for PMIC communication
[DEBUG]  pmic_efuse_setting: Set efuses in 10 msecs
[INFO ]  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ]  [RTC]rtc_boot,330: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ]  [RTC]rtc_enable_dcxo,66: con=0x486, osc32con=0xfe69, sec=0x0
[INFO ]  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
[INFO ]  [RTC]rtc_osc_init,62: osc32con val = 0xfe69
[INFO ]  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88244
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Zhigang Qin 2025-05-30 11:27:48 +08:00 • committed by Yidi Lin
commit 316f76635f
2 changed files with 12 additions and 2 deletions
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4
src/soc/mediatek/mt8189/Makefile.mk
View file

@ -28,7 +28,7 @@ romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c
romstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
romstage-y += ../common/pmif_spi.c pmif_spi.c
romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
romstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
ramstage-y += ../common/auxadc.c
@ -51,7 +51,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/mtk_fsp.c
ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
ramstage-y += ../common/pmif_spi.c pmif_spi.c
ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v1.c pmif_spmi.c
ramstage-y += ../common/pmif_spmi.c ../common/pmif_spmi_v2.c pmif_spmi.c
ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ../common/rtc_osc_init.c
ramstage-y += soc.c
ramstage-y += ../common/spm.c ../common/spm_v2.c spm.c

10
src/soc/mediatek/mt8189/pmif_spi.c
View file

@ -4,6 +4,11 @@
#include <gpio.h>
#include <soc/pmif_spi.h>
/* PMIF, SPI_MODE_CTRL */
DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9)
DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10)
DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11)
/* PMIF, SLEEP_PROTECTION_CTRL */
DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
@ -19,6 +24,11 @@ void pmif_spi_iocfg(void)
void pmif_spi_setting(struct pmif *arb)
{
SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl,
SPI_MODE_CTRL_SRCLK_EN, 0,
SPI_MODE_CTRL_SRVOL_EN, 0,
SPI_MODE_CTRL_PMIF_RDY, 1);
SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl,
SPM_SLEEP_REQ_SEL, 1,
SCP_SLEEP_REQ_SEL, 1);