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soc/mediatek/dp: Correct eDP register settings for dptx_v2

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SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from
old SoCs with dptx_v1. The formulas for register calculation are
different:
- The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp
on MT8196, while on older SoCs it is hsync + hbp.
- The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp
on MT8196, but vsync + vbp on earlier SoCs.
The current formula for MT8196 only works correctly when ha/va are
multiples of 4 and hfp/vfp are 0. The new formula fixes display errors
at resolutions like 1366x768 (ha=1366, hfp=48).
To distinguish these differences, an edp_version parameter is added.

Also update the following settings for correct configuration:
- Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous
incorrect setting.
- Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple
of 4 (such as 1366).

BUG=b:400886838
BRANCH=rauru
TEST=Check the display function on Navi

Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Vince Liu 2025-06-20 16:08:00 +08:00 • committed by Yidi Lin
commit cc0a410ff5
7 changed files with 13 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/mediatek/common/dp/dp_intf_v2.c
View file

@ -68,7 +68,7 @@ static void mtk_dvo_config_fb_size(const struct mtk_dvo *dvo, u32 width, u32 hei
mtk_dvo_mask(dvo, DVO_PIC_SIZE, width << PIC_HSIZE_SHIFT, PIC_HSIZE_MASK);
mtk_dvo_mask(dvo, DVO_PIC_SIZE, height << PIC_VSIZE_SHIFT, PIC_VSIZE_MASK);
mtk_dvo_mask(dvo, DVO_TGEN_H1, (width / 4) << HACT_SHIFT, HACT_MASK);
mtk_dvo_mask(dvo, DVO_TGEN_H1, DIV_ROUND_UP(width, 4) << HACT_SHIFT, HACT_MASK);
mtk_dvo_mask(dvo, DVO_TGEN_V1, height << VACT_SHIFT, VACT_MASK);
}

1
src/soc/mediatek/common/dp/dptx_common.c
View file

@ -253,6 +253,7 @@ void dptx_init_variable(struct mtk_dp *mtk_dp)
mtk_dp->has_dsc = false;
mtk_dp->has_fec = false;
mtk_dp->dsc_enable = false;
mtk_dp->edp_version = EDP_VERSION;
}
static inline bool dptx_check_res_sample_rate(const struct edid *edid)

8
src/soc/mediatek/common/dp/dptx_hal_common.c
View file

@ -107,7 +107,7 @@ void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable)
void dptx_hal_set_msa(struct mtk_dp *mtk_dp)
{
u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal;
u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal, val;
struct edid *edid = mtk_dp->edid;
va = edid->mode.va;
@ -150,13 +150,15 @@ void dptx_hal_set_msa(struct mtk_dp *mtk_dp)
DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal);
DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp);
DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, hsync);
DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp);
val = mtk_dp->edp_version == 1 ? hsync + hbp : hsync + hbp + hfp;
DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, val);
DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha);
/* vertical */
DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal);
DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, vfp);
DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync);
DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp);
val = mtk_dp->edp_version == 1 ? vsync + vbp : vsync + vbp + vfp;
DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, val);
DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va);
printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n",

2
src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h
View file

@ -178,6 +178,8 @@
#define MATRIX_BIT_MASK (0x3 << 8)
#define EXT_MATRIX_EN BIT(12)
#define EDP_VERSION 1
enum mtk_dpintf_out_bit_num {
MTK_DPINTF_OUT_BIT_NUM_8BITS,
MTK_DPINTF_OUT_BIT_NUM_10BITS,

2
src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h
View file

@ -165,6 +165,8 @@
#define DVO_BUF_SODI_HIGHT 0x230
#define DVO_BUF_SODI_LOW 0x234
#define EDP_VERSION 2
enum mtk_dvo_golden_setting_level {
MTK_DVO_FHD_60FPS_1920 = 0,
MTK_DVO_FHD_60FPS_2180,

1
src/soc/mediatek/common/dp/include/soc/dptx_common.h
View file

@ -215,6 +215,7 @@ struct mtk_dp {
bool enabled;
bool powered;
bool force_max_swing;
u8 edp_version;
};
int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid);

2
src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h
View file

@ -98,7 +98,7 @@
#define REG_35F0_DP_TRANS_P0 0x35F0
#define REG_360C_AUX_TX_P0 0x360C
#define REG_3614_AUX_TX_P0 0x3614
#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
#define REG_3618_AUX_TX_P0 0x3618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x200
#define REG_3620_AUX_TX_P0 0x3620