soc/mediatek/mt8189: Change msdcpll default freq to 384MHz

According to the eMMC specification, the maximum allowed source clock
frequency is 200MHz. Currently, a 416MHz source clock is used, which
after division results in 208MHz. This exceeds the spec limit.

Additionally, considering possible frequency fluctuations and desense
issues, 384MHz is a more reasonable and safer value. Limit the source
clock frequency to 384MHz to ensure compliance with the eMMC
specification and improve system stability.

BUG=b:396258620
BRANCH=none
TEST=echo fmeter > /proc/clkdbg ; cat /proc/clkdbg |grep msdcpll
30: fm_msdcpll_ck                : 383500

Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3c704b1200dd89a05476a5b14b75950aead51f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>

src/soc/mediatek/mt8189/include/soc/pll.h

@@ -524,7 +524,7 @@ enum {
 	TVDPLL1_HZ	= 594 * MHz,
 	TVDPLL2_HZ	= 594 * MHz,
 	ETHPLL_HZ	= 500 * MHz,
-	MSDCPLL_HZ	= 416 * MHz,
+	MSDCPLL_HZ	= 384 * MHz,
 	UFSPLL_HZ	= 594 * MHz,
 };