Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.
BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.
Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.
Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME
Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras
Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).
For more information please refer to #854345 (Intel CNDA).
Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
66 | #define INT32_MAX ((int32_t)0x7FFFFFFF)
| ^~~~~~~~~
[...]
129 | #define INT32_MAX (0x7FFFFFFF)
| ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```
Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.
Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Convert all PCI device and USB port references in the jasperlake_rvp
devicetree to use device aliases from the Jasperlake chipset.cb instead
of direct device/function numbers. This improves maintainability by
using symbolic names, and reduces file size by eliminating entries
which match those in the chipset devicetree.
Additionally, the p2sb device reference is dropped, as the correct state
(hidden) is set by the chipset devicetree.
TEST=Build jslrvp
Change-Id: I04fd2d1655f08fb0671deeeb55a3e88eb97b7f44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90902
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure all mipi_camera sensor configurations have both ssdb.lanes_used
and ssdb.link_used defined, and that these values correctly match the
corresponding (known good) CIO2 IPU port configuration:
- ssdb.lanes_used must match cio2_lanes_used = {x} for CAMx
- ssdb.link_used must match cio2_prt[x] for CAMx
Change-Id: Ifbf22c69d29c71138b7f59f08782d90425a09e30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add ssdb.rom_type and rom_address registers to board variants for MIPI
camera sensor SSDB settings, which are necessary for the Intel driver
stack under Windows and mainline Linux. A handful of boards, mostly not
released to the public, include a commented-out placeholder as ROM type
24C1024 is currently unsupported.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I16b44609c1b07ac686d67cc59b4b5311495117ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90486
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for Pantherlake LPCAMM T3 Reference Validation Platform:
- Define PTLP_LPCAMM_T3_RVP board ID (0x02)
- Add memory configuration for LPCAMM including DQ/DQS mapping
- Configure SPD information for LPCAMM modules using SMBus address 0x50
across all channels with MEM_TOPO_LP5_CAMM topology to enable SPD
detection
BUG=none
TEST=Boot LPCAMM T3 RVP and verify memory detection.
Change-Id: I17325241c105a5af5a97931be5c75a025b2bd7c8
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90139
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many boards were incorrectly using the VCM I2C address (0x0C) as the
SSDB vcm_type field value. These are two separate fields:
- ssdb.vcm_type: Enum identifying the VCM chip model (VCM_DW9714,
VCM_DW9808, etc.) used by drivers to select appropriate VCM functions
- vcm_address: I2C address of the VCM device (typically 0x0C)
Replace hardcoded "0x0C" values in ssdb.vcm_type with the correct enum
values based on the actual VCM device:
- VCM_DW9714 for boards using DW9714 VCMs
- VCM_DW9808 for boards using DW9768 VCMs (DW9768 doesn't have an enum,
but DW9808 has compatible register layout)
Add vcm_address = "0x0C" to all affected boards to properly specify
the I2C address separately from the VCM type.
This ensures the Windows and Linux camera drivers receive the correct
VCM type information needed for proper initialization and function
pointer selection.
TEST=tested with rest of patch train
Change-Id: I53a560b0b03a1fe49d35ad8238679cc130327ade
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <ericllai@google.com>
The SSDB platform field was unset on many boards, causing the driver
to default to PLAT_SKC (Skylake). This field is required for proper
camera sensor initialization and is validated by the driver.
Set the correct platform enum value based on the SoC.
TEST=tested with rest of patch train
Change-Id: I34e0aba0ba34dabcf25287ff04bc4251135ca09e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90196
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Include guards should cover the whole file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
The FNP4 power resource (minimum fan level) had both _ON and _OFF
methods setting the same state (\FLVL = 4), violating ACPI power
resource requirements where _OFF must transition to a state where
_STA eventually returns 0 (OFF).
This violation causes Windows to reject the thermal zone entirely due
to its stricter ACPI compliance checking, resulting in non-functional
fan control. Linux tolerates this bug, which is why it went unnoticed.
Since FAN4 represents the minimum cooling state with no lower state
to transition to, the correct implementation is to make _OFF a no-op.
This maintains proper ACPI state machine semantics: after _ON, _STA
returns 1; after _OFF, the system remains at minimum cooling (which
is already the lowest valid state).
This enables proper fan control operation on Windows while maintaining
Linux compatibility.
TEST=untested, but same as tested change on other mainboards in series.
Change-Id: I5d6c5f6cb8232b956bbd1be6220b8bb09c32b480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add firmware configuration support for SPD (Serial Presence Detect)
selection on Intel PTLRVP boards. This change allows dynamic memory
configuration based on fw_config fields instead of relying solely on
board ID detection.
BUG=None
TEST=Build and verify SPD selection works correctly on PTLRVP boards
with different memory configurations.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3cc45ad9813bef09718fe679bfafb700024586f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88255
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces changes to the ACPI implementation for the
PTLRVP mainboard by adding power meter support. It defines how the
PAC194x series devices are connected to the I2C controller and details
their configuration. Each device under scope \_SB.PCI0.I2C3 is given
specific methods to indicate its status, resource settings, and device
specific configurations via _DSM. This includes functionality to return
monitored power rail names, resistor values, EMI configurations, sample
frequencies, and Vbus multiplication factors. These changes enhance
the power management capabilities of the mainboard, allowing precise
monitoring and control over various power rails.
BUG=none
TEST=Verify power meter ACPI changes in DSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6e5d38500cac46187283481ef6f84215b14e927b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new Kconfig which tells the mainboard is using the "legacy" verb
table implementation. This is only needed during the transition towards
the reworked implementation, and will be removed once completed.
The Kconfigs were added manually and not with a script.
Change-Id: I3806cc8df4e244ee6542ad6796ccd9e36de557e5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89174
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit updates the DDR5 memory initialization parameters for the
Intel PTLRVP mainboard. Specifically, the ChannelToCkdQckMapping and
PhyClockToCkdDimm settings are overridden to ensure accurate mapping of
memory channels and PHY clocks to their respective Clock Driver and
DIMM connections.
BUG=none
TEST=Boot the PTLRVP board with DDR5 memory and verify memory
initialization.
Change-Id: I1be0a66a40e2613f10426dacd5494e345c5579db
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Camera sensor gets enumerated even if the hardware is not connected and
makes it available for the user, leading to a black screen when the user
tries to open the camera.
This commit changes the probing power state for the OV13B Camera Sensor
to the D0 Power State in order for the driver to validate the physical
hardware connection. This change helps prevent unnecessary enumeration
when hardware is not connected.
TEST=On a Fatcat device with an OV13B camera sensor disconnected, the OS
does not offer to use this video device.
Change-Id: Iabd8ffa6fd50367ff77325a2e1d9ae05e31eac93
Signed-off-by: Venturi Naveen <venturi.naveen@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
As per Intel document 853127, EPD_ON_GCD_OUT (previously GPP_A15)
is no longer available for other functions. Updated GPIO
configuration accordingly.
Reference: Intel doc 853127
BUG=none
TEST=Build and boot test on fatcat hardware
Change-Id: Ie4a3967ceecd10905ba0424d85d8f1392625bf16
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89103
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a wake configuration to the cnvi_bluetooth device for
all the ptlrvp board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4c17ca926a4409cedfaef24a802330ef463703ac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.
BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.
Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpClkReqSupport[] is a boolean, so use true/false.
Change-Id: I541ac5361dc0a929459edef7bb1f49c57b137c14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86281
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Granite Rapids SoC has 2 SKUs, a.k.a. GNR-AP and GNR-SP, which
use different FSP headers/binaries. Add Kconfig items to support
these SKU types.
Change-Id: Ie3a2d603f0a2c303e8f3c0911598742fbc25d73a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88897
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-by: Schumi Chu
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set disable_progress_bar to disable the memory progress bar for fatcat
board. Removed the memory progress bar feature to enhance performance.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar is
disable.
Change-Id: Ic303aa57843039f49130c09da0345f7e7573b0e5
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88613
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
While reviewing CB:87192 that deals with this option on another
mainboard, it was found that northbridge/intel/sandybridge
actually could not handle this option (present on Ivy Bridge
only anyway) properly. It would only factor 544MB into memory
calculations while telling IGD it can use 1024MB.
Until a fix can be implemented there, remove this option from
Ivy Bridge mainboards.
Change-Id: I0c87c52ef050cca54e050de3d41603c4ab29740b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88294
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces support for the H58G66BK7BX067 memory module
within the Intel PTLRVP mainboard variant. The changes include updates
to several configuration files to recognize and utilize this specific
memory module. The SPD source files and DRAM ID assignments have been
updated accordingly to integrate the new memory module into the build
system. This addition ensures compatibility and functionality with
the H58G66BK7BX067 memory module, allowing for expanded hardware
support and flexibility in memory configurations.
BUG=none
TEST=Build and verify memory module detection and initialization
on supported hardware configuration.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic281125dd40bbcef50d138e912e7557d6552eb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88177
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit eliminates the power limit constraints initially adopted
from the Fatcat board's codebase. These constraints are tailored for
factory-specific scenarios, which are irrelevant to the Intel Panther
Lake RVP (PTLRVP) board's use case.
Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/beechnutcity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: Ie115bd8e9044455185f82885a306849c509157bb
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87690
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/avenuecity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: I92589253915ad88bbb73736e10e7524b6be82499
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87689
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit addresses the GPIO configuration for DDR5 on Intel's
PTLRVP mainboard. Specifically, it extends support for the DDR5
configuration by adding a case for PTLP_DDR5_RVP in the GPIO
differential table function. This modification ensures proper handling
of GPIO settings when DDR5 memory is configured, thereby improving
system stability and compatibility.
BUG=none
TEST=Boot with DDR5 configuration.
Change-Id: I3745c0a25e84a0f41dced44613cfd638c12fb1d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87872
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Make use of the alias names defined in the chipset devicetree. Remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I79de952d95798aa3c241e7864223c63c0a72ce31
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83524
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit introduces the GPIO configuration support for the T4 LP5
Reference Validation Platform (RVP). It includes a table that outlines
the differences in GPIO configuration between the T3 LP5 RVP and T4 LP5
RVP. The GPIO differences are applied when the board ID is recognized as
T4.
BUG=none
TEST=Ensure the T4 RVP boots to the OS, then verify the GPIO pad
configurations by inspecting the output from /sys/kernel/debug/pinctrl.
Check that the GPIO PADs match the expected configuration for the T4
board.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ica870752bed2ba47c73d8fcd5f2f41b9cc6db65a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87447
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces support for the T4 LP5 board memory
configuration within the ptlrvp mainboard. The addition includes
defining the specific memory configurations such as data and strobe
signal mappings, early command training, and memory part ID
assignments. By implementing these changes, compatibility and
functionality are ensured for systems using the T4 LP5 board.
The memory configuration is specified for LP5 type memory with
detailed DQ and DQS mapping for different DDR channels. This
facilitates accurate signal routing and memory initialization.
Additionally, updates to associated Makefiles and documentation files
reflect these new memory parts (Hynix H58G56BK8BX068) and their IDs,
ensuring proper recognition and usage during system builds.
BUG=none
TEST=Build and verify system initialization on the T4 LP5 board with
the updated memory configuration. Confirm that memory training and
setup proceed correctly with the newly supported memory part.
Change-Id: Ia6e862af8c322fe4467465557c416d4171796e83
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87422
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the mainboard directory for Intel's ptlrvp variant, ensure that the
`variant.c` file is compiled during the ramstage build process. This
adjustment enables the execution of variant_update_soc_chip_config()
for ptlrvp in ramstage, addressing CNVi Wi-Fi-related issues.
BUG=None
TEST=Verify that variant.c is compiled correctly in ramstage for
ptlrvp.
Change-Id: Iec9591aac536abfdd36dfba8a8fea689830ee41a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87570
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces support for DDR5 memory configuration on the
PTL RVP DDR5 board. It adds the necessary board ID for PTLP_DDR5_RVP
and integrates a new DDR5 memory configuration within the variant
parameters. The memory configuration includes settings such as
resistor values, sagv values, early command training, and
DDR5-specific training parameters.
Additionally, SPD information retrieval is adapted to accommodate
DDR5-specific settings, such as DIMM module topology and SMBus
addresses.
BUG=none
TEST=Boot to OS with PTL RVP DDR5 board and verify memory
initialization.
Change-Id: I7e3bbb66edcbf4d4a10fcf6899156f125dc3d529
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87179
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as
of coreboot codebase commit 010cfa2842
("doc/internals/devicetree_language: multiple segment groups
supported").
Here is the list of imported commits:
- commit 9495063993 ("mainboard/google/fatcat: Fix SMBIOS Processor
upgrade info")
- commit 27f3427f4a ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin
for FPS")
- commit c41af2d43c ("mb/google/fatcat/var/fatcat: Update THC
Interrupt for Touchpad Development")
- commit b5dea9fa99 ("mb/google/fatcat/var/francka: Add Write Protect
GPIO to cros_gpios")
- commit ef80ccbc43 ("mb/google/fatcat: Disable EC software sync for
Microchip EC")
- commit 9f39d6ec5e ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for
felino and francka")
- commit eb85dfae1f ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for
francka and felino")
- commit 0fc2422e88 ("mb/google/fatcat: Implement S0ix hooks aka
`MS0X` method")
- commit 1fa5ab805b ("mb/google/fatcat: Remove unnecessary CNVi core
variables settings")
- commit 5c0340349e ("mb/google/fatcat: Rationalize Wi-Fi and
Bluetooth combinations")
- commit 275beb93db ("mb/google/fatcat: Conditionally check for barrel
charger")
- commit e9b020f02e ("mb/google/fatcat: Allow board-specific FSP-M UPD
override")
- commit 3a88eb8cb6 ("mb/google/fatcat: Enable HDA SDI based on FW
config")
- commit 0ac2058dbe ("mb/google/fatcat: Increase sagv_freq_mhz for
work point #1 to #3")
- commit 6e529e7c06 ("mb/google/fatcat: Add Intel Touch support for
touchscreen and touchpad")
Overall, these commits aim to improve the configuration, performance,
and compatibility of the Intel Panther Lake Reference Validation
Platform (PTLRVP) mainboard across various aspects, including processor
upgrade support, peripheral integration, power management, and audio
functionality.
TEST=Successful boot with a ptlrvp image on a Fatcat board.
Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87223
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds configurations for both external and internal EC
versions of the PTL RVP board. The changes involve updates to the
Kconfig files to select appropriate EC configurations based on the
specific PTL RVP variant. By organizing these options, it ensures
that the build system selects the right EC components and
configurations, aligning with the specific needs of the board version
in use.
The new configuration for external EC (`BOARD_INTEL_PTLRVP_CHROMEEC`)
enables Chrome EC related config options and enables TPM, whereas
Intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config
options and uses MOCK TPM.
BUG=none
TEST=Build the firmware for PTL RVP with both external and internal EC
settings, verifying that the correct components are included based on
the chosen configuration. Ensure that the board operates correctly
with the selected EC setup.
Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the Flashmap (FMAP) descriptor to allocate 18MB to
Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake
(PTL) Reference Validation Platform (RVP) coreboot is used with
several types of RVP boards, and this layout with a 14MB BIOS is
very convenient for debugging and creating coreboot for certain
use cases and testing purposes.
TEST=Build the ptlrvp variant (ES) and check if the flashmap of
the coreboot is updated correctly.
Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
FMAP should not contain information about the memory map.
Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"
for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.
tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.
Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.
The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.
Brya, zork, rex, fatcat, brox and dedede boards select
EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function.
BUG=b:396366352
TEST=Verify zork and brya boot log reports the correct the SKU ID
information
Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.
BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.
Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds initial dq mapping and spd data for LP5 memory
parts for GCS board. This also configures memory based on the board id.
Memory - LPDDR5x
Vendor/Model - H58G66BK8BX067
BUG=b:398880064
TEST=Boot to OS on GCS board.
Change-Id: I268ddf2d4b6361d9dabb217c4246cb6cc0e2144c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit introduces new board ID definitions for PTL-P and GCS in the
PTLRVP mainboard code. The changes involve updating the `romstage.c` and
`memory.c` files to handle these new board IDs, ensuring that memory
configuration is correctly initialized based on the detected board
type.
Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces the Intel Panther Lake (PTL) Reference Validation
Platform (RVP) mainboard definition. It is aligned with the Google
Fatcat mainboard in the coreboot codebase, with the commit hash
e2ea7f22c6.
Intel's proprietary platform, commonly referred to as PTLRVP, and
Google's Fatcat mainboard share a considerable degree of similarity in
their design and capabilities. Nevertheless, Intel faces unique
challenges and requires specific board configurations that Google does
not. Consequently, there is a necessity for a specialized mainboard
tailored to Intel's individual needs.
To maintain consistency with the Fatcat board definition, the Chrome OS
Board Information (CBI) firmware configuration aligns with that of
Google Fatcat. If necessary, new bits will be appended, starting from
the end of the 32-bit firmware configuration field.
BUG=b:398880064
TEST=The Intel PTLRVP board successfully boots to the operating System.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84564
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
