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mb/intel/ptlrvp: Configure CDCLK frequency for display

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Configure the Core Display Clock (CDCLK) frequency selection by setting
the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ptlrvp
baseboard devicetree. This ensures the display engine operates at
the required frequency for the panel to meet the hardware configuration.

BUG=b:458353982
TEST=Build and boot ptlrvp, verify display initialization.

Change-Id: I34abb742ab5d95da4d21ea22da2b1bc7270f1a9c
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Sowmya V 2026-02-17 17:04:29 +05:30 • committed by Subrata Banik
commit d0e139437a
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
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@ -83,6 +83,7 @@ chip soc/intel/pantherlake
register "pch_hda_idisp_codec_enable" = "true"
register "disable_progress_bar" = "true"
register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ"
device domain 0 on
device ref dtt on end