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mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3

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Update the SaGV frequency registers
- (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800".
- (`sagv_freq_mhz[2]`) in the devicetree from "6000" to "6400".
- (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800".

This change likely to improve the device performance.

BUG=b:328770565, b:407862619
TEST=Able to reduce the boot time by 18ms.

Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87087
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Subrata Banik 2025-04-02 08:07:56 +05:30
commit 0ac2058dbe
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
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@ -36,13 +36,13 @@ chip soc/intel/pantherlake
register "sagv_freq_mhz[0]" = "2400"
register "sagv_gear[0]" = "GEAR_4"
register "sagv_freq_mhz[1]" = "3200"
register "sagv_freq_mhz[1]" = "4800"
register "sagv_gear[1]" = "GEAR_4"
register "sagv_freq_mhz[2]" = "6000"
register "sagv_freq_mhz[2]" = "6400"
register "sagv_gear[2]" = "GEAR_4"
register "sagv_freq_mhz[3]" = "6400"
register "sagv_freq_mhz[3]" = "6800"
register "sagv_gear[3]" = "GEAR_4"
# Enable s0ix