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mb/intel/ptlrvp: Remove power limit constraints

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This commit eliminates the power limit constraints initially adopted
from the Fatcat board's codebase. These constraints are tailored for
factory-specific scenarios, which are irrelevant to the Intel Panther
Lake RVP (PTLRVP) board's use case.

Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2025-06-17 13:15:20 -07:00 • committed by Jérémy Compostella
commit ea3cc3231c
2 changed files with 0 additions and 63 deletions
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1
src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
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@ -1,4 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only
romstage-y += memory.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ramstage.c

62
src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
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@ -1,62 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <ec/google/chromeec/ec.h>
/*
* SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
*/
const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_1_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 25000,
.pl2_min_power = 50000,
.pl2_max_power = 50000,
.pl4_power = 65000
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_1_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 25000,
.pl2_min_power = 50000,
.pl2_max_power = 50000,
.pl4_power = 65000
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 25000,
.pl2_min_power = 50000,
.pl2_max_power = 50000,
.pl4_power = 65000
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.pl1_min_power = 10000,
.pl1_max_power = 25000,
.pl2_min_power = 50000,
.pl2_max_power = 50000,
.pl4_power = 65000
},
};
void baseboard_devtree_update(void)
{
/* Don't optimize the power limit if booting with barrel attached */
if (CONFIG(BOARD_INTEL_MODEL_PTLRVP) && google_chromeec_is_barrel_charger_present())
return;
if (!google_chromeec_is_battery_present())
variant_update_cpu_power_limits(power_optimized_limits,
ARRAY_SIZE(power_optimized_limits));
}