mb/intel/coffelake_rvp: Make use of chipset devicetree
Make use of the alias names defined in the chipset devicetree. Remove devices which are equal to the ones from the chipset devicetree. Change-Id: I79de952d95798aa3c241e7864223c63c0a72ce31 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83524 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
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6 changed files with 54 additions and 94 deletions
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@ -43,33 +43,18 @@ chip soc/intel/cannonlake
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register "s0ix_enable" = "false"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.5 on end # SDCard
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 1e.0 on end # UART #0
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on
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device ref igpu on end
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device ref dptf on end
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device ref thermal on end
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device ref xhci on end
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device ref sdxc on end
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device ref uart0 on end
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device ref lpc_espi on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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end
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device ref hda on end
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device ref smbus on end
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end
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end
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@ -61,15 +61,11 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[9]" = "9"
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device domain 0 on
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C #4 (Not available on PCH-H)
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device pci 19.1 off end # I2C #5 (Not available on PCH-H)
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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device ref i2c0 on end
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device ref i2c1 on end
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device ref sata on end
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device ref uart2 on end
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device ref emmc on end
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device ref pcie_rp1 on # x4 SLOT1
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register "PcieRpSlotImplemented[0]" = "1"
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end
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@ -79,9 +75,6 @@ chip soc/intel/cannonlake
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device ref pcie_rp9 on
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.6 on end # GbE
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device ref gbe on end
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end
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end
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@ -63,21 +63,19 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[10]" = "10"
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device domain 0 on
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device pci 14.3 on
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.3 on end # I2C #3
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C #4 (Not available on PCH-H)
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device pci 19.1 off end # I2C #5 (Not available on PCH-H)
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref i2c2 on end
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device ref i2c3 on end
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device ref sata on end
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device ref uart2 on end
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device ref emmc on end
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device ref pcie_rp1 on
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register "PcieRpSlotImplemented[0]" = "1"
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end
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@ -102,7 +100,6 @@ chip soc/intel/cannonlake
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device ref pcie_rp21 on # x4 SLOT 2
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register "PcieRpSlotImplemented[20]" = "1"
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end
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device pci 1e.1 off end # UART #1
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device pci 1f.6 on end # GbE
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device ref gbe on end
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end
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end
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@ -38,16 +38,15 @@ chip soc/intel/cannonlake
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}"
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device domain 0 on
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device pci 14.3 on
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 on
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end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref i2c3 on
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chip drivers/i2c/max98373
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register "interleave_mode" = "1"
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register "vmon_slot_no" = "4"
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@ -57,12 +56,10 @@ chip soc/intel/cannonlake
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register "name" = ""MAXR""
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device i2c 32 on end
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end
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end # I2C #3
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device pci 17.0 off end # SATA
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device pci 19.0 on end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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end
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device ref i2c4 on end
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device ref uart2 on end
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device ref emmc on end
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device ref pcie_rp1 on # x4 SLOT1
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register "PcieRpSlotImplemented[0]" = "1"
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end
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@ -72,9 +69,5 @@ chip soc/intel/cannonlake
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device ref pcie_rp9 on
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.6 off end # GbE
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end
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end
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@ -59,22 +59,19 @@ chip soc/intel/cannonlake
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register "sdcard_cd_gpio" = "GPP_G5"
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device domain 0 on
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device pci 14.3 on
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 14.5 on end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 17.0 on end # SATA
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device pci 19.0 on end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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end
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device ref sdxc on end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref sata on end
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device ref i2c4 on end
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device ref uart2 on end
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device ref emmc on end
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device ref pcie_rp1 on # x4 SLOT1
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register "PcieRpSlotImplemented[0]" = "1"
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end
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@ -84,7 +81,6 @@ chip soc/intel/cannonlake
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device ref pcie_rp9 on
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1e.1 off end # UART #1
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device pci 1f.6 on end # GbE
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device ref gbe on end
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end
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end
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@ -44,21 +44,18 @@ chip soc/intel/cannonlake
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register "sdcard_cd_gpio" = "GPP_G5"
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device domain 0 on
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device pci 14.3 on
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 17.0 on end # SATA
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device pci 19.0 on end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref sata on end
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device ref i2c4 on end
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device ref uart2 on end
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device ref emmc on end
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device ref pcie_rp1 on # x4 SLOT1
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register "PcieRpSlotImplemented[0]" = "1"
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end
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@ -68,7 +65,6 @@ chip soc/intel/cannonlake
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device ref pcie_rp9 on
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1e.1 off end # UART #1
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device pci 1f.6 on end # GbE
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device ref gbe on end
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end
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end
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