mb/intel/coffelake_rvp: Make use of chipset devicetree

Make use of the alias names defined in the chipset devicetree. Remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: I79de952d95798aa3c241e7864223c63c0a72ce31
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83524
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Felix Singer 2024-07-18 00:35:12 +02:00 committed by Felix Singer
commit eec228987e
6 changed files with 54 additions and 94 deletions

View file

@ -43,33 +43,18 @@ chip soc/intel/cannonlake
register "s0ix_enable" = "false"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA Thermal device
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.5 on end # SDCard
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 1e.0 on end # UART #0
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on
device ref igpu on end
device ref dptf on end
device ref thermal on end
device ref xhci on end
device ref sdxc on end
device ref uart0 on end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
end
device ref hda on end
device ref smbus on end
end
end

View file

@ -61,15 +61,11 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[9]" = "9"
device domain 0 on
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4 (Not available on PCH-H)
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device ref i2c0 on end
device ref i2c1 on end
device ref sata on end
device ref uart2 on end
device ref emmc on end
device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
@ -79,9 +75,6 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.6 on end # GbE
device ref gbe on end
end
end

View file

@ -63,21 +63,19 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[10]" = "10"
device domain 0 on
device pci 14.3 on
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end # CNVi wifi
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4 (Not available on PCH-H)
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c2 on end
device ref i2c3 on end
device ref sata on end
device ref uart2 on end
device ref emmc on end
device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
end
@ -102,7 +100,6 @@ chip soc/intel/cannonlake
device ref pcie_rp21 on # x4 SLOT 2
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
device ref gbe on end
end
end

View file

@ -38,16 +38,15 @@ chip soc/intel/cannonlake
}"
device domain 0 on
device pci 14.3 on
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end # CNVi wifi
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 on
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c3 on
chip drivers/i2c/max98373
register "interleave_mode" = "1"
register "vmon_slot_no" = "4"
@ -57,12 +56,10 @@ chip soc/intel/cannonlake
register "name" = ""MAXR""
device i2c 32 on end
end
end # I2C #3
device pci 17.0 off end # SATA
device pci 19.0 on end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
end
device ref i2c4 on end
device ref uart2 on end
device ref emmc on end
device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
@ -72,9 +69,5 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.6 off end # GbE
end
end

View file

@ -59,22 +59,19 @@ chip soc/intel/cannonlake
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device pci 14.3 on
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end # CNVi wifi
device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.0 on end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
end
device ref sdxc on end
device ref i2c0 on end
device ref i2c1 on end
device ref sata on end
device ref i2c4 on end
device ref uart2 on end
device ref emmc on end
device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
@ -84,7 +81,6 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
device ref gbe on end
end
end

View file

@ -44,21 +44,18 @@ chip soc/intel/cannonlake
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device pci 14.3 on
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end # CNVi wifi
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.0 on end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
end
device ref i2c0 on end
device ref i2c1 on end
device ref sata on end
device ref i2c4 on end
device ref uart2 on end
device ref emmc on end
device ref pcie_rp1 on # x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
@ -68,7 +65,6 @@ chip soc/intel/cannonlake
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
device ref gbe on end
end
end