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sb/intel: Convert get_gpio() to gpio_get()

Browse source 
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2025-07-21 08:19:39 +02:00 • committed by Matt DeVillier
commit 69364fc9e0
26 changed files with 90 additions and 95 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
View file

@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <option.h>
#include <device/device.h>
#include <southbridge/intel/common/gpio.h>
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
#include <option.h>
#include <southbridge/intel/common/gpio.h>
#include "chip.h"
/*
@ -20,7 +20,7 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
dev->enabled = 0;
config = dev->chip_info;
if (!config || (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED)) {
if (!config || (gpio_get(config->detect_gpio) == DGPU_NOT_INSTALLED)) {
printk(BIOS_DEBUG, "Hybrid graphics: Not installed\n");
return;
}

14
src/drivers/lenovo/hybrid_graphics/romstage.c
View file

@ -1,12 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h>
#include <option.h>
#include <device/device.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <option.h>
#include <gpio.h>
#include <types.h>
#include <southbridge/intel/common/gpio.h>
#include "hybrid_graphics.h"
#include "chip.h"
@ -31,7 +31,7 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
}
config = dev->chip_info;
if (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED) {
if (gpio_get(config->detect_gpio) == DGPU_NOT_INSTALLED) {
printk(BIOS_DEBUG, "Hybrid graphics:"
" No discrete GPU present.\n");
*enable_igd = true;

4
src/ec/lenovo/h8/bluetooth.c
View file

@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
#include <gpio.h>
#include <option.h>
#include <types.h>
@ -34,7 +34,7 @@ bool h8_has_bdc(const struct device *dev)
return true;
}
if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
if (gpio_get(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
printk(BIOS_INFO, "H8: BDC installed\n");
return true;
}

4
src/ec/lenovo/h8/wwan.c
View file

@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
#include <gpio.h>
#include <option.h>
#include <types.h>
@ -32,7 +32,7 @@ bool h8_has_wwan(const struct device *dev)
return true;
}
if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
if (gpio_get(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
printk(BIOS_INFO, "H8: WWAN installed\n");
return true;
}

6
src/mainboard/dell/optiplex_9020/mainboard.c
View file

@ -4,8 +4,8 @@
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <gpio.h>
#include <option.h>
#include <southbridge/intel/common/gpio.h>
#include "sch5555_ec.h"
static void mainboard_enable(struct device *dev)
@ -269,8 +269,8 @@ static uint8_t get_chassis_type(void)
uint8_t gpio_chassis_type;
// Read chassis type from GPIO
gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
get_gpio(17) << 1 | get_gpio(1);
gpio_chassis_type = gpio_get(70) << 3 | gpio_get(38) << 2 |
gpio_get(17) << 1 | gpio_get(1);
printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);

34
src/mainboard/dell/snb_ivb_workstations/mainboard.c
View file

@ -5,8 +5,8 @@
#include <device/device.h>
#include <device/pci_ops.h>
#include <drivers/intel/gma/int15.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <superio/smsc/sch5545/sch5545.h>
#include <baseboard/sch5545_ec.h>
@ -56,10 +56,10 @@ static void mainboard_enable(struct device *dev)
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
pin_sts = get_gpio(GPIO_CHASSIS_ID0);
pin_sts |= get_gpio(GPIO_CHASSIS_ID1) << 1;
pin_sts |= get_gpio(GPIO_CHASSIS_ID2) << 2;
pin_sts |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
pin_sts = gpio_get(GPIO_CHASSIS_ID0);
pin_sts |= gpio_get(GPIO_CHASSIS_ID1) << 1;
pin_sts |= gpio_get(GPIO_CHASSIS_ID2) << 2;
pin_sts |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
printk(BIOS_DEBUG, "Chassis type: ");
switch (pin_sts) {
@ -88,15 +88,15 @@ static void mainboard_enable(struct device *dev)
break;
}
pin_sts = get_gpio(GPIO_BOARD_REV0);
pin_sts |= get_gpio(GPIO_BOARD_REV1) << 1;
pin_sts |= get_gpio(GPIO_BOARD_REV2) << 2;
pin_sts = gpio_get(GPIO_BOARD_REV0);
pin_sts |= gpio_get(GPIO_BOARD_REV1) << 1;
pin_sts |= gpio_get(GPIO_BOARD_REV2) << 2;
printk(BIOS_DEBUG, "Board revision: %d\n", pin_sts);
pin_sts = get_gpio(GPIO_SKU0);
pin_sts |= get_gpio(GPIO_SKU1) << 1;
pin_sts |= get_gpio(GPIO_SKU2) << 2;
pin_sts = gpio_get(GPIO_SKU0);
pin_sts |= gpio_get(GPIO_SKU1) << 1;
pin_sts |= gpio_get(GPIO_SKU2) << 2;
printk(BIOS_DEBUG, "SKU ID is %d:", pin_sts);
switch (pin_sts) {
@ -115,15 +115,15 @@ static void mainboard_enable(struct device *dev)
}
printk(BIOS_DEBUG, "VGA cable %sconnected\n",
get_gpio(GPIO_VGA_CABLE_DET_L) ? "dis" : "");
gpio_get(GPIO_VGA_CABLE_DET_L) ? "dis" : "");
printk(BIOS_DEBUG, "Flexbay %sattached to internal USB 2.0 header\n",
get_gpio(FLEXBAY_HEADER_CABLE_DET_L) ? "not " : "");
gpio_get(FLEXBAY_HEADER_CABLE_DET_L) ? "not " : "");
printk(BIOS_DEBUG, "Password clear jumper %sactive\n",
get_gpio(GPIO_PSWD_CLR) ? "in" : "");
gpio_get(GPIO_PSWD_CLR) ? "in" : "");
if (!get_gpio(GPIO_FRONT_PANEL_PRESENT_L)) {
if (!gpio_get(GPIO_FRONT_PANEL_PRESENT_L)) {
printk(BIOS_DEBUG, "Front panel cable connected\n");
} else {
printk(BIOS_WARNING, "Front panel cable not connected!\n");
@ -132,7 +132,7 @@ static void mainboard_enable(struct device *dev)
printk(BIOS_WARNING, "Check the front panel cable!\n");
}
if (!get_gpio(GPIO_INTRUDER_CABLE_DET_L)) {
if (!gpio_get(GPIO_INTRUDER_CABLE_DET_L)) {
printk(BIOS_DEBUG, "Intruder cable connected\n");
} else {
printk(BIOS_WARNING, "Intruder cable not connected!\n");
@ -140,7 +140,7 @@ static void mainboard_enable(struct device *dev)
printk(BIOS_WARNING, "Check the intruder cable!\n");
}
if (!get_gpio(GPIO_USB_HEADER_DET_L)) {
if (!gpio_get(GPIO_USB_HEADER_DET_L)) {
printk(BIOS_DEBUG, "Front USB 3.0 cable connected\n");
} else {
printk(BIOS_WARNING, "Front USB 3.0 cable not connected!\n");

10
src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c
View file

@ -6,7 +6,7 @@
#include <cpu/x86/msr.h>
#include <console/console.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <southbridge/intel/common/gpio.h>
#include <gpio.h>
#include <superio/smsc/sch5545/sch5545.h>
#include <superio/smsc/sch5545/sch5545_emi.h>
@ -300,10 +300,10 @@ static uint8_t get_chassis_type(void)
{
uint8_t chassis_id;
chassis_id = get_gpio(GPIO_CHASSIS_ID0);
chassis_id |= get_gpio(GPIO_CHASSIS_ID1) << 1;
chassis_id |= get_gpio(GPIO_CHASSIS_ID2) << 2;
chassis_id |= get_gpio(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
chassis_id = gpio_get(GPIO_CHASSIS_ID0);
chassis_id |= gpio_get(GPIO_CHASSIS_ID1) << 1;
chassis_id |= gpio_get(GPIO_CHASSIS_ID2) << 2;
chassis_id |= gpio_get(GPIO_FRONT_PANEL_CHASSIS_DET_L) << 3;
/* This mapping will determine which EC init sequence to use */
switch (chassis_id) {

6
src/mainboard/google/auron/chromeos.c
View file

@ -2,10 +2,10 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/chromeos.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "onboard.h"
@ -28,7 +28,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(CROS_WP_GPIO);
return gpio_get(CROS_WP_GPIO);
}
static const struct cros_gpio cros_gpios[] = {
@ -40,5 +40,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
return !get_gpio(EC_IN_RW_GPIO);
return !gpio_get(EC_IN_RW_GPIO);
}

6
src/mainboard/google/beltino/chromeos.c
View file

@ -3,8 +3,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -23,12 +23,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
static const struct cros_gpio cros_gpios[] = {

5
src/mainboard/google/butterfly/chromeos.c
View file

@ -3,9 +3,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/quanta/ene_kb3940q/ec.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -31,7 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return !get_gpio(WP_GPIO);
return !gpio_get(WP_GPIO);
}
int get_lid_switch(void)

6
src/mainboard/google/jecht/chromeos.c
View file

@ -4,10 +4,10 @@
#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/chromeos.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
@ -24,12 +24,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
static const struct cros_gpio cros_gpios[] = {

6
src/mainboard/google/link/chromeos.c
View file

@ -2,8 +2,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -29,7 +29,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
@ -41,5 +41,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
return !get_gpio(GPIO_EC_IN_RW);
return !gpio_get(GPIO_EC_IN_RW);
}

9
src/mainboard/google/parrot/chromeos.c
View file

@ -4,9 +4,8 @@
#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -33,17 +32,17 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
return get_gpio(GPIO_LID);
return gpio_get(GPIO_LID);
}
int get_write_protect_state(void)
{
return !get_gpio(GPIO_SPI_WP);
return !gpio_get(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
static const struct cros_gpio cros_gpios[] = {

6
src/mainboard/google/slippy/chromeos.c
View file

@ -2,8 +2,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -20,7 +20,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
@ -32,5 +32,5 @@ DECLARE_CROS_GPIOS(cros_gpios);
int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
return !get_gpio(14);
return !gpio_get(14);
}

5
src/mainboard/google/stout/chromeos.c
View file

@ -5,9 +5,8 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
@ -36,7 +35,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return !get_gpio(GPIO_SPI_WP);
return !gpio_get(GPIO_SPI_WP);
}
int get_lid_switch(void)

6
src/mainboard/intel/baskingridge/chromeos.c
View file

@ -3,8 +3,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -33,13 +33,13 @@ int get_recovery_mode_switch(void)
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
return get_gpio(GPIO_REC_MODE);
return gpio_get(GPIO_REC_MODE);
}
int get_write_protect_state(void)
{
/* Write protect is active low, so invert it here */
return !get_gpio(GPIO_SPI_WP);
return !gpio_get(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {

8
src/mainboard/intel/dcp847ske/mainboard.c
View file

@ -3,16 +3,16 @@
#include <console/console.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/common/gpio.h>
#include <gpio.h>
static void mainboard_enable(struct device *dev)
{
printk(BIOS_DEBUG, "Memory voltage: %s\n",
get_gpio(8) ? "1.35V" : "1.5V");
gpio_get(8) ? "1.35V" : "1.5V");
printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n",
get_gpio(22) ? "normal (1-2)" : "setup (2-3)");
gpio_get(22) ? "normal (1-2)" : "setup (2-3)");
printk(BIOS_DEBUG, "mSATA: %s\n",
get_gpio(35) ? "present" : "absent");
gpio_get(35) ? "present" : "absent");
install_intel_vga_int15_handler(
GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,

6
src/mainboard/intel/emeraldlake2/chromeos.c
View file

@ -3,8 +3,8 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -30,13 +30,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_recovery_mode_switch(void)
{
/* Recovery: GPIO22, active low */
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
int get_write_protect_state(void)
{
/* Write protect is active low, so invert it here */
return !get_gpio(GPIO_SPI_WP);
return !gpio_get(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {

7
src/mainboard/lenovo/t400/romstage.c
View file

@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <southbridge/intel/common/gpio.h>
#include <northbridge/intel/gm45/gm45.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <gpio.h>
#include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/common/gpio.h>
static void hybrid_graphics_init(sysinfo_t *sysinfo)
{
@ -24,7 +25,7 @@ void get_mb_spd_addrmap(u8 spd_addrmap[4])
void mb_pre_raminit_setup(sysinfo_t *sysinfo)
{
if (CONFIG(BOARD_LENOVO_R500)) {
int use_integrated = get_gpio(21);
int use_integrated = gpio_get(21);
printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n",
use_integrated ? "integrated" : "discrete");
if (use_integrated) {

2
src/mainboard/lenovo/x1_carbon_gen1/early_init.c
View file

@ -10,7 +10,7 @@ static unsigned int get_spd_index(void)
unsigned int spd_index = get_gpios(spd_gpio_vector);
/* 4gb model = 0, 8gb model = 1 */
/* int extended_memory_version = get_gpio(44); */
/* int extended_memory_version = gpio_get(44); */
/*
* So far there is no need to parse gpio 44, as the 4GiB use

6
src/mainboard/samsung/lumpy/chromeos.c
View file

@ -4,8 +4,8 @@
#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -34,12 +34,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
int get_lid_switch(void)

6
src/mainboard/samsung/stumpy/chromeos.c
View file

@ -4,8 +4,8 @@
#include <boot/coreboot_tables.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -32,12 +32,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
return gpio_get(GPIO_SPI_WP);
}
int get_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
return !gpio_get(GPIO_REC_MODE);
}
int get_power_switch(void)

7
src/southbridge/intel/common/gpio.c
View file

@ -3,9 +3,10 @@
#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_type.h>
#include <gpio.h>
#include <stdint.h>
#include "gpio.h"
#include "southbridge/intel/common/gpio.h"
#define MAX_GPIO_NUMBER 75 /* zero based */
@ -84,7 +85,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
/*
* return current gpio level.
*/
int get_gpio(int gpio_num)
int gpio_get(gpio_t gpio_num)
{
static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3};
u16 gpio_base = get_gpio_base();
@ -111,7 +112,7 @@ unsigned int get_gpios(const int *gpio_num_array)
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
if (get_gpio(gpio))
if (gpio_get(gpio))
vector |= bitmask;
bitmask <<= 1;
}

2
src/southbridge/intel/common/gpio.h
View file

@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
/* Configure GPIOs with mainboard provided settings */
void setup_pch_gpios(const struct pch_gpio_map *gpio);
/* get GPIO pin value */
int get_gpio(int gpio_num);
/*
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.

5
src/southbridge/intel/lynxpoint/lp_gpio.c
View file

@ -5,6 +5,7 @@
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
#include "pch.h"
#include "lp_gpio.h"
@ -99,7 +100,7 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[])
outl(pirq2apic, gpio_base + GPIO_PIRQ_APIC_EN);
}
int get_gpio(int gpio_num)
int gpio_get(gpio_t gpio_num)
{
u16 gpio_base = get_gpio_base();
@ -121,7 +122,7 @@ unsigned int get_gpios(const int *gpio_num_array)
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
if (get_gpio(gpio))
if (gpio_get(gpio))
vector |= bitmask;
bitmask <<= 1;
}

3
src/southbridge/intel/lynxpoint/lp_gpio.h
View file

@ -157,9 +157,6 @@ struct pch_lp_gpio_map {
/* Configure GPIOs with mainboard provided settings */
void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
/* Get GPIO pin value */
int get_gpio(int gpio_num);
/* Set GPIO pin value */
void set_gpio(int gpio_num, int value);