mb/intel/ptlrvp: Add DQ mapping and SPD for GCS board

This patch adds initial dq mapping and spd data for LP5 memory
parts for GCS board. This also configures memory based on the board id.

Memory - LPDDR5x
Vendor/Model - H58G66BK8BX067

BUG=b:398880064
TEST=Boot to OS on GCS board.

Change-Id: I268ddf2d4b6361d9dabb217c4246cb6cc0e2144c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-3.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 
 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP5X,
@@ -16,7 +17,14 @@ const struct mb_cfg *__weak variant_memory_params(void)
 
 int __weak variant_memory_sku(void)
 {
-	return 0;
+	uint8_t board_id = get_rvp_board_id();
+	size_t spd_index;
+
+	printk(BIOS_INFO, "Board ID is 0x%x\n", board_id);
+
+	spd_index = (board_id == GCS_32GB || board_id == GCS_64GB) ? 1 : 0;
+
+	return spd_index;
 }
 
 bool __weak variant_is_half_populated(void)

src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c

@@ -5,6 +5,66 @@
 #include <soc/romstage.h>
 #include <soc/meminit.h>
 
+static const struct mb_cfg gcs_mem_config = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  14,  8,  15,  9,  10,  12,  11,  13, },
+			.dq1 = {  6,  7,  5,  4,  1,  3,  0,  2, },
+		},
+		.ddr1 = {
+			.dq0 = {  0,  1,  3,  4,  2,  5,  6,  7, },
+			.dq1 = {  12,  13,  14,  15,  10,  11,  8,  9, },
+		},
+		.ddr2 = {
+			.dq0 = {  10,  9,  8,  11,  12,  15,  14,  13, },
+			.dq1 = {  1,  3,  0,  2,  6,  7,  5,  4, },
+		},
+		.ddr3 = {
+			.dq0 = {  5,  6,  7,  4,  2,  3,  1,  0,},
+			.dq1 = {  15,  14,  10,  11,  12,  13,  9,  8, },
+		},
+		.ddr4 = {
+			.dq0 = {  8,  10,  9,  11,  13,  12,  14,  15, },
+			.dq1 = {  4,  5,  1,  3,  7,  0,  2,  6, },
+		},
+		.ddr5 = {
+			.dq0 = {  1,  0,  3,  2,  6,  7,  4,  5, },
+			.dq1 = {  11,  14,  10,  13,  9,  12,  8,  15, },
+		},
+		.ddr6 = {
+			.dq0 = {  10,  8,  15,  9,  13,  12,  14,  11, },
+			.dq1 = {  3,  4,  7,  0,  2,  5,  6,  1, },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  7,  3,  6,  5,  4,  },
+			.dq1 = {  11,  15,  10,  8,  13,  9,  12,  14, },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.lp_ddr_dq_dqs_re_training = 1,
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
 static const struct mb_cfg lp5_mem_config = {
 	.type = MEM_TYPE_LP5X,
 
@@ -72,9 +132,10 @@ const struct mb_cfg *variant_memory_params(void)
 	switch (board_id) {
 	case PTLP_LP5_T3_RVP:
 	case PTLP_LP5_T4_RVP:
+		return &lp5_mem_config;
 	case GCS_32GB:
 	case GCS_64GB:
-		return &lp5_mem_config;
+		return &gcs_mem_config;
 	default:
 		die("Unknown board id = 0x%x\n", board_id);
 		break;
@@ -84,5 +145,5 @@ const struct mb_cfg *variant_memory_params(void)
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
-	spd_info->cbfs_index = 0;
+	spd_info->cbfs_index = variant_memory_sku();
 }

src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk

@@ -5,3 +5,4 @@
 
 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 0(0b0000)  Parts = H58G56BK7BX068
+SPD_SOURCES += spd/lp5/set-0/spd-10.hex      # ID = 1(0b0001)  Parts = H58G66BK8BX067

src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt

@@ -5,3 +5,4 @@
 
 DRAM Part Name                 ID to assign
 H58G56BK7BX068                 0 (0000)
+H58G66BK8BX067                 1 (0001)

src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt

@@ -10,3 +10,4 @@
 
 # Part Name
 H58G56BK7BX068
+H58G66BK8BX067