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mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS

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This updates the Flashmap (FMAP) descriptor to allocate 18MB to
Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake
(PTL) Reference Validation Platform (RVP) coreboot is used with
several types of RVP boards, and this layout with a 14MB BIOS is
very convenient for debugging and creating coreboot for certain
use cases and testing purposes.

TEST=Build the ptlrvp variant (ES) and check if the flashmap of
the coreboot is updated correctly.

Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Jamie Ryu 2025-03-27 23:00:30 -07:00 • committed by Matt DeVillier
commit 3e0cfc6222
1 changed files with 5 additions and 9 deletions
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14
src/mainboard/intel/ptlrvp/chromeos.fmd
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@ -1,20 +1,17 @@
FLASH 32M {
SI_ALL 8M {
SI_ALL 18M {
SI_DESC 16K
SI_EC 576K
SI_ME
SI_ME_PAD@16M 2M
}
SI_BIOS 24M {
RW_SECTION_A 8M {
SI_BIOS 14M {
RW_SECTION_A 4M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
# This section starts at the 16M boundary in SPI flash.
# PTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 8M {
RW_SECTION_B 4M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
@ -33,7 +30,6 @@ FLASH 32M {
RW_NVRAM(PRESERVE) 24K
}
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {