Configure power state thresholds (PS1, PS2, PS3) according to the
platform design specification. These thresholds define current limits
at which the voltage regulator domains transition between different
power states for optimal power management.
Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ] (MAILBOX) PS1Threshold = 80 (1/4 Amp)
[SPEW ] (MAILBOX) PS2Threshold = 20 (1/4 Amp)
[SPEW ] (MAILBOX) PS3Threshold = 4 (1/4 Amp)
Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 835b63980d, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging.
BUG=b:490040385
Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This reverts commit 42210fdb28, which was causing the
ocelot DDR5 RVP to not boot. Reverting until further debugging.
BUG=b:490040385
Change-Id: I5185a036ccbd6cca19eb1a3fd762686ed03919e8
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The eDP AUX controller currently sets the NO_SEND_STOP flag for all
I2C-over-AUX transactions. This prevents the controller from issuing
an I2C STOP condition, which is required for proper completion of
multi-block (extended) EDID reads.
Update edp_msg_fifo_tx() to only set the EDP_AUX_TRANS_CTRL_NO_SEND_STOP
flag when the DP_AUX_I2C_MOT (Middle-of-Transaction) bit is set in the
request. This allows the I2C transaction to correctly finalize with a
STOP condition when MOT is not present, enabling successful reads of
EDID extension blocks.
BUG=none
TEST=Verify extended EDID is correctly read on Google/Quartz.
Change-Id: I4b637a750ef16148895332abfd9ca202b5a35408
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.
For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.
Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.
Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set IA voltage regulator to use IRMS mode with 28 second time window
for more accurate thermal design current measurement.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with the following
VR parameter
[SPEW ] TdcMode[0]:0x1
[SPEW ] TdcMode[1]:0x0
[SPEW ] TdcMode[2]:0x0
[SPEW ] TdcMode[3]:0x0
[SPEW ] TdcTimeWindow[0]:0x6D60
[SPEW ] TdcTimeWindow[1]:0x0
[SPEW ] TdcTimeWindow[2]:0x0
[SPEW ] TdcTimeWindow[3]:0x0
Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce mtk_mipi_panel_poweroff() in common display layer and
mtk_dsi_panel_poweroff() in DSI driver. The DSI mode flags are
saved during init and reused for the power-off command path.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: Ic684822bc5f20d3e2f5ce3d44035c902a2b44184
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91432
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The commit 7072f42c08f7 ("soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE
from SRAM to SRAM_L2C") move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
causes elog_handle_watchdog_tombstone (BS_POST_DEVICE, BS_ON_ENTRY) to
be invoked after mtk_mmu_disable_l2c_sram. As a result, the watchdog
event magic value in WATCHDOG_TOMBSTONE is cleared before it can be
processed, which is incorrect behavior.
So we refactor the mtk_mmu_disable_l2c_sram to be called as a boot state
entry (BS_POST_DEVICE, BS_ON_EXIT) instead of directly from soc_init.
This ensures that mtk_mmu_disable_l2c_sram will be executed after
elog_handle_watchdog_tombstone.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout (triggered via echo > /dev/watchdog)
TEST=cbmem logs preserved on WDT timeout
Change-Id: I69ef567ab73f2f7006bb249cb577f377d4720909
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout
Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/pantherlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Meteor Lake, making
it an ideal candidate for consolidation.
Change-Id: I749eea246fdc7ab89848ed4160c61666e8944095
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/meteorlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Panther Lake, making
it an ideal candidate for consolidation.
Change-Id: Id0c3bde3b721b7a3e497711cfc6dd21efbfda4c5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This introduces a common finalize implementation for Intel SoCs that
consolidates the nearly identical finalize.c files across Meteor Lake
and Panther Lake platforms.
The implementation includes:
- pch_finalize(): TCO lockdown and PMC status clearing
- tbt_finalize(): Disable Thunderbolt PCIe root ports bus master
- sa_finalize(): Lock system agent PAM regions when coreboot handles
chipset lockdown
- heci_finalize(): Set HECI to D0i3 and optionally disable HECI1
- soc_finalize(): Main finalization sequence coordinating all the above
This consolidation eliminates duplicate code and ensures consistent
finalization behavior across platforms. Alder Lake is intentionally
excluded as it has additional platform-specific camera clock (ISCLK)
configuration that would complicate the common implementation.
The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_FINALIZE
Kconfig option.
Platforms that will use this common implementation:
- Meteor Lake
- Panther Lake
Change-Id: I4dd9ccf7e14fecdded92da6bf366e6ff56d866a4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91227
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/elkhartlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I635347f15e35ec8e69c24edcec8c45c55a496ffd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/jasperlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Ia039b25b21b4af5912dd5e8af9ef06a66c00a7bd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/cannonlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: If5a70a0e05c50ab893ba8861e200b078982dfad9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91213
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/tigerlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I1bf9d4eeab0fecbb33d122a32ecdeef85af059fa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/pantherlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I9bd0dae5bbfc0ec2e9101e848de2037760314456
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/meteorlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I0ad75bbeb1fad7352b2b898487a5b54eff496d0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/alderlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Iebaf5bafd5a97dde37ffc435b2ad8b6a8dcfecd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
This introduces a common implementation of do_global_reset() that
uses CSE (Converged Security Engine) with PMC (Power Management
Controller) fallback. This implementation is identical across 7
Intel client platforms.
The function attempts to request a global reset from the CSE first,
which is the preferred method. If CSE is unavailable or the request
fails, it falls back to enabling PMC-based global reset and
triggering a full reset.
This consolidates the global reset handling and eliminates duplicate
code across multiple platforms. The common implementation is enabled
via the SOC_INTEL_COMMON_RESET_GLOBAL_RESET_CSE_PMC Kconfig option.
Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Cannon Lake
- Jasper Lake
- Elkhart Lake
Change-Id: Ida59bc2df483db5397ee043f66fdee56508bd0df
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91208
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/pantherlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Panther Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Meteor Lake.
Change-Id: I9becbedbb1bcbc19f60d3ebb024dd5e43c7cee29
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91207
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/meteorlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Meteor Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Panther Lake.
Change-Id: Iecccc482f04d85cfec738dd57dc1473eaf82cfcc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific lockdown.c with the common PMC lockdown
driver introduced in the previous commit.
Changes:
- Remove src/soc/intel/alderlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to ST_PG_FDIS1 in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Alder Lake uses the ST_PG_FDIS1 register (0x1e20) for ST_FDIS_LOCK,
which differs from newer platforms that use GEN_PMCON_B. This
difference is handled through the PMC_FDIS_LOCK_REG define.
Change-Id: Ic80aca618dcbe5a4fef54f4802e6f4ce6f4ebd44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91205
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation to unify the Haswell and Broadwell codebases, move the
remaining Broadwell SoC code to the northbridge folder.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I5bde032ee824a90328a78403ea03d39ad20f2b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The PCH split was done many moons ago, in order to unify two codebases
with overlapping hardware support: Haswell + Lynx Point and Broadwell.
The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I29235b47970f81b5db6717801f2ab771ff980476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 4c4bd3cd97 ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bd ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.
Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When SOC_INTEL_COMPLIANCE_TEST_MODE is enabled, disable PCIe clock
gating and power gating to prevent the controller from entering power
management states that would interfere with PCIe compliance testing.
This ensures stable operation during PCIe TX compliance tests by
keeping the PCIe controller in an active state throughout the test
process.
Affected/Verified Platforms:
- PTL: Lapis, Ruby
- WCL: Matsu, Ocicat, Kodkod
BUG=b:451560515
TEST="Run PCIe Compliance TX test successfully"
Change-Id: I92f442d24219af78310ce04b782735beed9c58e6
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90325
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend get_microcode_info() to return the microcode size.
This is being used in the following commit which uses the size
to copy the microcode update to RAM in order to speed up MPinit.
Depending on the SPI flash interface speed, the microcode size and
the number of APs this can improve boot time by seconds.
Since microcode size isn't used yet this is not a functional change.
Change-Id: I1385e04c56e1411f0847a1c201c17e460c957477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move loading of microcode to pre_mp_init() as found on other
Intel CPU drivers. There’s no need to cache the microcode location
since intel_microcode_find() already caches it.
No function change, thus untested.
Change-Id: I05bbb074d189594027916c6a3b04270bd3b6edd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90892
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a common low battery poweroff implementation in
soc/mediatek/common/low_battery.c. This implementation checks
if a low battery shutdown is needed and triggers a poweroff
via Chrome EC if necessary.
Also enable this for mt8196 in ramstage.
BUG=b:424707341
TEST=The FW draws low battery indicator and powers off the DUT after 5
seconds.
TEST=Use `elogtool list` and see `Low Battery boot | Power Off`
Change-Id: I2fcd242fbf26bdebc4acfb477c95c381adf645f5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91431
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The current VBUS enablement logic was found to be unnecessary for
USB host functionality on x1p42100. Forcing VBUS power via the PMIC's
OTG buck is not required for the current hardware configuration and
could lead to incorrect power state management.
Remove the enable_vbus_ss() function and associated SCHG DCDC
register definitions from the SoC driver. This streamlines the
USB initialization path to focus solely on PHY and controller
setup.
TEST=Verify USB detection in the depthcharge on Google/Quartz.
Change-Id: Ie30878802831419f3d70ea921f7f46a262db99bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set the SCHG_DCDC_OTG_CFG register to 0x26 during USB initialization
to ensure the OTG buck is correctly configured for host mode.
TEST=Verify USB detection in the depthcharge on Google/Quartz.
Change-Id: If76be8b7210fc86f473bfd77eb56718f28f19eae
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add the SoC hook to initialize SPI TPM decoding. Without the additional
programming an attempt to talk to SPI TPM hangs the platform when the
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is set. If TPM is initialized in
ramstage, the OpenSIL programs the SPI TPM decoding properly and the
issue is not observed.
TEST=Select TPM_MEASURED_BOOT_INIT_BOOTBLOCK and enable
TPM_MEASURED_BOOT on Gigabyte MZ33-AR1, and observe the platform does
not hang in bootblock.
Change-Id: I2e6c0aad31fd0335e0d16111ed4894a12d2ba497
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Move the SOC_I2C_DEVFN(n) macro definitions that were duplicated in a
separate "for common code" section at the end of multiple platform
pci_devs.h files.
Platforms affected:
- Alder Lake
- Cannon Lake
- Elkhart Lake
- Jasper Lake
- Skylake
- Tiger Lake
Change-Id: Ie3b3e6a25b0dba1beeadad1ab9acf59cafdbcf4a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Migrate Tiger Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/tigerlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Tiger Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Panther Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/pantherlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Panther Lake uses PCI_DEV_PMC as the PMC device identifier.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I32bf4b678e7edda598319086acccc4983edcbe3e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91296
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/meteorlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Meteor Lake uses PCI_DEV_PMC as the PMC device identifier.
Change-Id: Ia21a6ee0c6fbee6d4ffcfce5fdbe9b3bdf5fcece
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91295
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/alderlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Alder Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Icbbc7af25e73e952c9b5f811cf0bbe01efe3ae94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Add a common implementation of SMI handler code for PCH client platforms
to reduce code duplication across Alder Lake, Meteor Lake, Panther Lake,
and Tiger Lake platforms.
This implementation consolidates:
- smihandler_soc_disable_busmaster(): Skip disabling PMC bus master
- southbridge_smi array: Standard SMI handler mappings
The common driver uses a platform-specific macro that must be defined in
each platform's soc/pci_devs.h header:
- SOC_PMC_DEV: PMC PCI device identifier
This change enables consolidation of nearly identical smihandler.c files
across four platforms, reducing duplication by approximately 100+ lines.
Change-Id: I9ecb65b7ea4feafb8acbaf5798bbeaeb80b7c24a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91293
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Panther Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I3ee9630a6b15d7b02776ff633a3cff0766a8915b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91239
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: Ieb62ffac95550a0ae8607a3a9ae76e0f6ff0ac35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This adds a common PM utility driver for modern Intel platforms that
share consistent PM register layouts.
The driver consolidates power management utility functions that were
previously duplicated across multiple Intel SoC platforms. This
includes functions for:
- SMI/TCO/GPE status bit decoding
- PMC MMIO base address access
- RTC failure detection
- Sleep state management
- Power state structure population
- After-G3 power state configuration
- GPE configuration retrieval using generic config_t
The GPE configuration function (soc_get_gpi_gpe_configs) uses the
generic config_t typedef that each platform defines, allowing complete
code reuse without platform-specific shims.
This common driver is controlled by the Kconfig option
SOC_INTEL_COMMON_FEATURE_PMUTIL and is built for all boot stages.
Change-Id: I45b829b7c18ee66474457df5523069f930806b35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/elkhartlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: I59d9cb1b37bca2c682e2bf87fc3f5b24c34fb920
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
