haswell/broadwell: Move CPU bus ops to CPU code

Commit 4c4bd3cd97 ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bd ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.

Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/haswell_init.c

@@ -606,6 +606,13 @@ static const struct cpu_device_id cpu_table[] = {
 	CPU_TABLE_END
 };
 
+struct device_operations haswell_cpu_bus_ops = {
+	.read_resources   = noop_read_resources,
+	.set_resources    = noop_set_resources,
+	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
+};
+
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,

src/mainboard/google/auron/devicetree.cb

@@ -15,7 +15,7 @@ chip soc/intel/broadwell
 	register "ec_present" = "true"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 
 		register "s0ix_enable" = "true"
 	end

src/mainboard/google/jecht/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/broadwell
 	register "dq_pins_interleaved" = "true"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on

src/mainboard/hp/elitebook_820_g2/devicetree.cb

@@ -2,7 +2,7 @@
 
 chip soc/intel/broadwell
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops

src/mainboard/intel/wtm2/devicetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	register "gpu_dp_b_hotplug" = "0x06"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops

src/mainboard/purism/librem_bdw/devicetree.cb

@@ -21,7 +21,7 @@ chip soc/intel/broadwell
 	}"
 
 	chip cpu/intel/haswell
-		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops

src/northbridge/intel/haswell/northbridge.c

@@ -534,13 +534,6 @@ static const struct pci_driver mc_driver_hsw __pci_driver = {
 	.devices = mc_pci_device_ids,
 };
 
-struct device_operations haswell_cpu_bus_ops = {
-	.read_resources   = noop_read_resources,
-	.set_resources    = noop_set_resources,
-	.init             = mp_cpu_bus_init,
-	.acpi_fill_ssdt   = generate_cpu_entries,
-};
-
 struct chip_operations northbridge_intel_haswell_ops = {
 	.name = "Intel Haswell integrated Northbridge",
 };

src/soc/intel/broadwell/northbridge.c

@@ -406,13 +406,6 @@ struct device_operations broadwell_pci_domain_ops = {
 #endif
 };
 
-struct device_operations broadwell_cpu_bus_ops = {
-	.read_resources   = noop_read_resources,
-	.set_resources    = noop_set_resources,
-	.init             = mp_cpu_bus_init,
-	.acpi_fill_ssdt   = generate_cpu_entries,
-};
-
 static void broadwell_init_pre_device(void *chip_info)
 {
 	broadwell_run_reference_code();