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soc/qualcomm/x1p42100: Configure OTG buck for USB host

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Set the SCHG_DCDC_OTG_CFG register to 0x26 during USB initialization
to ensure the OTG buck is correctly configured for host mode.

TEST=Verify USB detection in the depthcharge on Google/Quartz.

Change-Id: If76be8b7210fc86f473bfd77eb56718f28f19eae
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2026-03-02 18:53:11 +05:30 • committed by Subrata Banik
commit 2c58402339
2 changed files with 14 additions and 0 deletions
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1
src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
View file

@ -114,6 +114,7 @@
#define OTG_STATE_ENABLED 0x02
#define OTG_STATUS_TIMEOUT_MS 20
#define OTG_STATUS_POLL_DELAY_MS 2
#define OTG_BUCK_CFG 0x26
/* Type-C register offsets */
#define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B

13
src/soc/qualcomm/x1p42100/usb/usb.c
View file

@ -495,6 +495,15 @@ static bool get_usb_typec_polarity(const struct dwc3_controller_config *config)
return (misc_status & CCOUT_INVERT_POLARITY) == CCOUT_INVERT_POLARITY;
}
/*
* Configures OTG buck for host mode
* @config: Controller configuration containing SMB slave address
*/
static void usb_configure_otg_buck(const struct dwc3_controller_config *config)
{
spmi_write8(SPMI_ADDR(config->smb_slave_addr, SCHG_DCDC_OTG_CFG), OTG_BUCK_CFG);
}
/* Initialization of DWC3 Core and PHY */
static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
{
@ -587,6 +596,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n");
high_speed_only_primary = true;
}
/* Configure OTG buck */
usb_configure_otg_buck(&prim_config);
/* Enable VBUS for C0 */
enable_vbus_ss(&prim_config);
udelay(50);
@ -618,6 +629,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n");
high_speed_only_secondary = true;
}
/* Configure OTG buck */
usb_configure_otg_buck(&sec_config);
/* Enable VBUS for C1 */
enable_vbus_ss(&sec_config);
udelay(50);