soc/intel/broadwell/pch: Move to sb/intel/wildcatpoint

The PCH split was done many moons ago, in order to unify two codebases
with overlapping hardware support: Haswell + Lynx Point and Broadwell.
The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point.

This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".

Change-Id: I29235b47970f81b5db6717801f2ab771ff980476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/devicetree.cb

@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# EC range is 0x800-0x9ff
 			register "gen1_dec" = "0x00fc0801"
 			register "gen2_dec" = "0x00fc0901"

src/mainboard/google/auron/dsdt.asl

@@ -17,7 +17,7 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
@@ -26,7 +26,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}

src/mainboard/google/auron/variants/auron_paine/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"

src/mainboard/google/auron/variants/auron_yuna/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "sata_devslp_disable" = "0x1"
 
 			register "sio_i2c0_voltage" = "1" # 1.8V

src/mainboard/google/auron/variants/gandof/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"

src/mainboard/google/auron/variants/lulu/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	}"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "sata_port0_gen3_tx" = "0x72"
 
 			# Set I2C0 to 1.8V

src/mainboard/google/jecht/devicetree.cb

@@ -21,7 +21,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on end # vga controller
 		device pci 03.0 on end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# SuperIO range is 0x700-0x73f
 			register "gen2_dec" = "0x003c0701"
 

src/mainboard/google/jecht/dsdt.asl

@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include <variant/acpi/thermal.asl>
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		}
 	}
 

src/mainboard/hp/elitebook_820_g2/devicetree.cb

@@ -24,7 +24,7 @@ chip soc/intel/broadwell
 		end
 		device pci 03.0 on end # Mini-HD audio
 
-		chip soc/intel/broadwell/pch # Wildcat Point PCH
+		chip southbridge/intel/wildcatpoint # Wildcat Point PCH
 			device pci 13.0 off end # Smart Sound Audio DSP
 			device pci 14.0 on  end # xHCI Controller
 			device pci 15.0 off end # Serial I/O DMA

src/mainboard/hp/elitebook_820_g2/dsdt.asl

@@ -17,7 +17,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 	#include <soc/intel/common/acpi/acpi_wake_source.asl>
 
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
@@ -25,7 +25,7 @@ DefinitionBlock(
 	Device (\_SB.PCI0)
 	{
 		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-		#include <soc/intel/broadwell/pch/acpi/pch.asl>
+		#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 }

src/mainboard/intel/wtm2/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end	# vga controller
 		device pci 03.0 on  end	# mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x00000400"
 			register "gpe0_en_2" = "0x00000000"

src/mainboard/intel/wtm2/dsdt.asl

@@ -18,7 +18,7 @@ DefinitionBlock(
 	#include "acpi/platform.asl"
 
 	// global NVS and variables
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <soc/intel/broadwell/acpi/device_nvs.asl>
 
 	// CPU
@@ -28,7 +28,7 @@ DefinitionBlock(
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 		}
 	}
 

src/mainboard/purism/librem_bdw/devicetree.cb

@@ -29,7 +29,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
 			register "gen1_dec" = "0x00000381"
 

src/mainboard/purism/librem_bdw/dsdt.asl

@@ -12,14 +12,14 @@ DefinitionBlock(
 {
 	#include <acpi/dsdt_top.asl>
 	#include <soc/intel/broadwell/acpi/platform.asl>
-	#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
+	#include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
 	Scope (\_SB) {
 		Device (PCI0)
 		{
 			#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-			#include <soc/intel/broadwell/pch/acpi/pch.asl>
+			#include <southbridge/intel/wildcatpoint/acpi/pch.asl>
 			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 		}
 	}

src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/broadwell
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# Port 0 is HDD
 			# Port 3 is M.2 NGFF
 			register "sata_port_map" = "0x9"

src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb

@@ -3,7 +3,7 @@ chip soc/intel/broadwell
 	register "dq_pins_interleaved" = "true"
 
 	device domain 0 on
-		chip soc/intel/broadwell/pch
+		chip southbridge/intel/wildcatpoint
 			# Port 0 is HDD
 			# Port 1 is M.2 NGFF
 			register "sata_port_map" = "0x3"

src/soc/intel/broadwell/Kconfig

@@ -10,7 +10,7 @@ config SOC_INTEL_BROADWELL
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT
 	select TCO_SPACE_NOT_YET_SPLIT
-	select INTEL_LYNXPOINT_LP
+	select SOUTHBRIDGE_INTEL_WILDCATPOINT
 	help
 	  Intel Broadwell and Haswell ULT support.
 
@@ -117,6 +117,4 @@ config REFCODE_BLOB_FILE
 
 endif # HAVE_REFCODE_BLOB
 
-source "src/soc/intel/broadwell/pch/Kconfig"
-
 endif

src/soc/intel/broadwell/pch/Makefile.mk

@@ -1,45 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-bootblock-y += bootblock.c
-
-ramstage-y += adsp.c
-romstage-y += early_pch.c
-ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-y += finalize.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-verstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-smm-y      += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
-ramstage-y += hda.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
-romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
-ramstage-y += fadt.c
-ramstage-y += lpc.c
-ramstage-y += me.c
-ramstage-y += me_status.c
-romstage-y += me_status.c
-ramstage-y += pch.c
-romstage-y += pch.c
-ramstage-y += pcie.c
-ramstage-y += pmutil.c
-romstage-y += pmutil.c
-smm-y      += pmutil.c
-verstage-y += pmutil.c
-romstage-y += power_state.c
-ramstage-y += ramstage.c
-ramstage-y += sata.c
-ramstage-y += serialio.c
-ramstage-y += ../../../../southbridge/intel/lynxpoint/smbus.c
-ramstage-y += smi.c
-smm-y      += smihandler.c
-bootblock-y += usb_debug.c
-romstage-y += usb_debug.c
-ramstage-y += usb_debug.c
-ramstage-y += usb_ehci.c
-ramstage-y += usb_xhci.c
-smm-y      += usb_xhci.c
-
-bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/iobp.c
-bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart_init.c
-all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c
-smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c

src/southbridge/intel/wildcatpoint/Kconfig

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config INTEL_LYNXPOINT_LP
+config SOUTHBRIDGE_INTEL_WILDCATPOINT
 	bool
 	select ACPI_COMMON_MADT_IOAPIC
 	select ACPI_COMMON_MADT_LAPIC
@@ -14,6 +14,7 @@ config INTEL_LYNXPOINT_LP
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select INTEL_LYNXPOINT_LP
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_RESET
@@ -23,6 +24,12 @@ config INTEL_LYNXPOINT_LP
 	select SPI_FLASH
 	select TCO_SPACE_NOT_YET_SPLIT
 
+if SOUTHBRIDGE_INTEL_WILDCATPOINT
+
+# Placeholder
+config INTEL_LYNXPOINT_LP
+	bool
+
 config EHCI_BAR
 	hex
 	default 0xd8000000
@@ -72,3 +79,5 @@ config DISABLE_ME_PCI
 	  Disable and hide the ME PCI interface during finalize stage of boot.
 	  This will prevent the OS (and userspace apps) from interacting with
 	  the ME via the PCI interface after boot.
+
+endif

src/southbridge/intel/wildcatpoint/Makefile.mk

@@ -0,0 +1,50 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y)
+
+bootblock-y += bootblock.c
+
+ramstage-y += adsp.c
+romstage-y += early_pch.c
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += finalize.c
+ramstage-y += ../lynxpoint/lp_gpio.c
+romstage-y += ../lynxpoint/lp_gpio.c
+verstage-y += ../lynxpoint/lp_gpio.c
+smm-y      += ../lynxpoint/lp_gpio.c
+ramstage-y += hda.c
+ramstage-y += ../lynxpoint/hda_verb.c
+ramstage-y += ../lynxpoint/iobp.c
+romstage-y += ../lynxpoint/iobp.c
+ramstage-y += fadt.c
+ramstage-y += lpc.c
+ramstage-y += me.c
+ramstage-y += me_status.c
+romstage-y += me_status.c
+ramstage-y += pch.c
+romstage-y += pch.c
+ramstage-y += pcie.c
+ramstage-y += pmutil.c
+romstage-y += pmutil.c
+smm-y      += pmutil.c
+verstage-y += pmutil.c
+romstage-y += power_state.c
+ramstage-y += ramstage.c
+ramstage-y += sata.c
+ramstage-y += serialio.c
+ramstage-y += ../lynxpoint/smbus.c
+ramstage-y += smi.c
+smm-y      += smihandler.c
+bootblock-y += usb_debug.c
+romstage-y += usb_debug.c
+ramstage-y += usb_debug.c
+ramstage-y += usb_ehci.c
+ramstage-y += usb_xhci.c
+smm-y      += usb_xhci.c
+
+bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/iobp.c
+bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart_init.c
+all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
+smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c
+
+endif

src/southbridge/intel/wildcatpoint/adsp.c

@@ -11,13 +11,13 @@
 #include <soc/device_nvs.h>
 #include <soc/pch.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <stdbool.h>
 
 static void adsp_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	u32 tmp32;
 

src/southbridge/intel/wildcatpoint/chip.h

@@ -5,7 +5,7 @@
 
 #include <types.h>
 
-struct soc_intel_broadwell_pch_config {
+struct southbridge_intel_wildcatpoint_config {
 	/* GPE configuration */
 	uint32_t gpe0_en_1;
 	uint32_t gpe0_en_2;

src/southbridge/intel/wildcatpoint/early_pch.c

@@ -11,7 +11,7 @@
 #include <soc/pm.h>
 #include <soc/rcba.h>
 #include <soc/romstage.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 
 static void pch_route_interrupts(void)
 {
@@ -56,7 +56,7 @@ static void pch_enable_lpc(void)
 	if (!dev || !dev->chip_info)
 		return;
 
-	const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+	const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);

src/southbridge/intel/wildcatpoint/lpc.c

@@ -17,7 +17,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <acpi/acpigen.h>
 #include <southbridge/intel/common/rtc.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
@@ -162,7 +162,7 @@ static void pch_power_options(struct device *dev)
 	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
 	if (dev->chip_info) {
-		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+		const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 		/* GPE setup based on device tree configuration */
 		enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
@@ -326,7 +326,7 @@ static void pch_enable_mphy(void)
 
 static void pch_init_deep_sx(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+	const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 
 	if (!config)
 		return;
@@ -575,7 +575,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
 
 	/* LPC Generic IO Decode range. */
 	if (dev->chip_info) {
-		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+		const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info;
 		pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
 		pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);

src/southbridge/intel/wildcatpoint/me.c

@@ -25,7 +25,7 @@
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -948,7 +948,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 /* Check whether ME is present and do basic init */
 static void intel_me_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	me_bios_path path = intel_me_path(dev);
 	me_bios_payload mbp_data;
 	int mbp_ret;

src/southbridge/intel/wildcatpoint/pch.c

@@ -196,7 +196,7 @@ static void broadwell_pch_enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations soc_intel_broadwell_pch_ops = {
+struct chip_operations southbridge_intel_wildcatpoint_ops = {
 	.name = "Intel Broadwell PCH",
 	.enable_dev = &broadwell_pch_enable_dev,
 };

src/southbridge/intel/wildcatpoint/pcie.c

@@ -12,7 +12,7 @@
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <types.h>
@@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev)
 		root_port_config_update_gbe_port();
 
 		pci_or_config8(dev, 0xe2, 3 << 4);
-		const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+		const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 		rpc.coalesce = config->pcie_port_coalesce;
 	}
 
@@ -435,7 +435,7 @@ static void pcie_add_0x0202000_iobp(u32 reg)
 
 static void pch_pcie_early(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	int do_aspm = 0;
 	int rp = root_port_number(dev);
 

src/southbridge/intel/wildcatpoint/sata.c

@@ -9,7 +9,7 @@
 #include <delay.h>
 #include <soc/rcba.h>
 #include <soc/sata.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 
 static inline u32 sir_read(struct device *dev, int idx)
@@ -26,7 +26,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
 
 static void sata_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	u32 reg32;
 	u8 *abar;
 	u16 reg16;
@@ -259,7 +259,7 @@ static void sata_init(struct device *dev)
 static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	u16 map = 0x0060;
 
 	map |= (config->sata_port_map ^ 0xf) << 8;

src/southbridge/intel/wildcatpoint/serialio.c

@@ -12,7 +12,7 @@
 #include <soc/pch.h>
 #include <soc/rcba.h>
 #include <soc/serialio.h>
-#include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/wildcatpoint/chip.h>
 #include <southbridge/intel/lynxpoint/iobp.h>
 #include <types.h>
 
@@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode)
 
 static void serialio_init(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct southbridge_intel_wildcatpoint_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	int sio_index = -1;