erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/pantherlake: Disable PCIe PM in compliance test mode

Browse source 
When SOC_INTEL_COMPLIANCE_TEST_MODE is enabled, disable PCIe clock
gating and power gating to prevent the controller from entering power
management states that would interfere with PCIe compliance testing.

This ensures stable operation during PCIe TX compliance tests by
keeping the PCIe controller in an active state throughout the test
process.

Affected/Verified Platforms:
  - PTL: Lapis, Ruby
  - WCL: Matsu, Ocicat, Kodkod

BUG=b:451560515
TEST="Run PCIe Compliance TX test successfully"

Change-Id: I92f442d24219af78310ce04b782735beed9c58e6
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90325
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Simon Yang 2025-12-02 14:42:12 +08:00 • committed by Matt DeVillier
commit e0715bc0f9
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/pantherlake/fsp_params.c
View file

@ -589,6 +589,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table());
for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
s_cfg->PcieClockGating[i] = 0;
s_cfg->PciePowerGating[i] = 0;
}
if (!(enable_mask & BIT(i)))
continue;
const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];