soc/intel/meteorlake: Use common pmutil driver
Migrate Meteor Lake to use the common PMC utility driver instead of maintaining platform-specific pmutil.c code. This change: - Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig - Removes platform-specific pmutil.c - Removes pmutil.c from Makefile.mk The common driver provides all necessary functionality through the generic config_t interface, eliminating ~290 lines of duplicated code. Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This commit is contained in:
Jeremy Compostella
Matt DeVillier
parent
f0be882d9f
commit
2eb37453e5
5 changed files with 6 additions and 291 deletions
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@ -89,6 +89,7 @@ config SOC_INTEL_METEORLAKE
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select SOC_INTEL_COMMON_FEATURE
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select SOC_INTEL_COMMON_FEATURE_ESPI
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select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
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select SOC_INTEL_COMMON_FEATURE_PMUTIL
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select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
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select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
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select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
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@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += pmutil.c
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all-y += gpio.c
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bootblock-y += bootblock/bootblock.c
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@ -44,7 +43,6 @@ ramstage-y += soc_info.c
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smm-y += elog.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += soc_info.c
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smm-y += xhci.c
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@ -150,9 +150,6 @@ struct chipset_power_state {
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/* Get base address PMC memory mapped registers. */
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uint8_t *pmc_mmio_regs(void);
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/* Get base address IOE.PMC memory mapped registers. */
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uint8_t *ioe_pmc_mmio_regs(void);
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/* Get base address of TCO I/O registers. */
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uint16_t smbus_tco_regs(void);
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@ -5,6 +5,11 @@
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#include <soc/iomap.h>
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#include <soc/pm.h>
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static uint8_t *ioe_pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
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}
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static void ioe_pmc_read_resources(struct device *dev)
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{
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/* Add the fixed MMIO resource */
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@ -1,286 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Helper functions for dealing with power management registers
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* and the differences between PCH variants.
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*/
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#define __SIMPLE_DEVICE__
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#include <acpi/acpi_pm.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <gpio.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/tco.h>
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#include <intelpch/espi.h>
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#include <security/vboot/vbnv.h>
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#include <soc/gpe.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <static.h>
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#include <types.h>
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/*
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* SMI
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*/
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const char *const *soc_smi_sts_array(size_t *a)
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{
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static const char *const smi_sts_bits[] = {
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[BIOS_STS_BIT] = "BIOS",
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[LEGACY_USB_STS_BIT] = "LEGACY_USB",
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[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
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[APM_STS_BIT] = "APM",
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[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
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[PM1_STS_BIT] = "PM1",
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[GPE0_STS_BIT] = "GPE0",
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[GPIO_STS_BIT] = "GPI",
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[MCSMI_STS_BIT] = "MCSMI",
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[DEVMON_STS_BIT] = "DEVMON",
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[TCO_STS_BIT] = "TCO",
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[PERIODIC_STS_BIT] = "PERIODIC",
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[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
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[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
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[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
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[MONITOR_STS_BIT] = "MONITOR",
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[SPI_SMI_STS_BIT] = "SPI",
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[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
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[ESPI_SMI_STS_BIT] = "ESPI_SMI",
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};
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*a = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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/*
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* TCO
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*/
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const char *const *soc_tco_sts_array(size_t *a)
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{
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI",
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[1] = "SW_TCO",
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[2] = "TCO_INT",
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[3] = "TIMEOUT",
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[7] = "NEWCENTURY",
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[8] = "BIOSWR",
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[9] = "DMISCI",
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[10] = "DMISMI",
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[12] = "DMISERR",
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[13] = "SLVSEL",
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[16] = "INTRD_DET",
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[17] = "SECOND_TO",
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[18] = "BOOT",
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[20] = "SMLINK_SLV"
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};
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*a = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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/*
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* GPE0
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*/
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const char *const *soc_std_gpe_sts_array(size_t *a)
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{
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static const char *const gpe_sts_bits[] = {
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[1] = "HOTPLUG",
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[2] = "SWGPE",
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[6] = "TCO_SCI",
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[7] = "SMB_WAK",
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[9] = "PCI_EXP",
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[10] = "BATLOW",
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[11] = "PME",
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[12] = "ME",
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[13] = "PME_B0",
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[14] = "eSPI",
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[15] = "GPIO Tier-2",
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[16] = "LAN_WAKE",
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[18] = "WADT"
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};
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*a = ARRAY_SIZE(gpe_sts_bits);
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return gpe_sts_bits;
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}
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void pmc_set_disb(void)
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{
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/* Set the DISB after DRAM init */
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uint8_t disb_val;
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/* Only care about bits [23:16] of register GEN_PMCON_A */
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uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
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disb_val = read8(addr);
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disb_val |= (DISB >> 16);
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/* Don't clear bits that are write-1-to-clear */
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disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
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write8(addr, disb_val);
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}
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/*
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* PMC controller gets hidden from PCI bus
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* during FSP-Silicon init call. Hence PWRMBASE
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* can't be accessible using PCI configuration space
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* read/write.
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*/
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uint8_t *pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
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}
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uint8_t *ioe_pmc_mmio_regs(void)
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{
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return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
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}
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t)pmc_mmio_regs();
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}
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uint32_t *soc_pmc_etr_addr(void)
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{
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return (uint32_t *)(soc_read_pmc_base() + ETR);
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}
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static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config)
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{
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bool all_zero = (config->pmc_gpe0_dw0 == 0) &&
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(config->pmc_gpe0_dw1 == 0) &&
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(config->pmc_gpe0_dw2 == 0);
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/* Check if all values are different AND not all zero */
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bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
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(config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
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(config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
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assert(all_different || all_zero);
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}
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void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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{
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DEVTREE_CONST struct soc_intel_meteorlake_config *config;
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config = config_of_soc();
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pmc_gpe0_different_values(config);
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/* Assign to out variable */
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*dw0 = config->pmc_gpe0_dw0;
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*dw1 = config->pmc_gpe0_dw1;
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*dw2 = config->pmc_gpe0_dw2;
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}
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static int rtc_failed(uint32_t gen_pmcon_b)
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{
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return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
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}
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int soc_get_rtc_failed(void)
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{
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const struct chipset_power_state *ps;
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if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
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return 1;
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return rtc_failed(ps->gen_pmcon_b);
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}
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int vbnv_cmos_failed(void)
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{
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return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
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}
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static inline int deep_s3_enabled(void)
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{
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uint32_t deep_s3_pol;
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deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
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return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
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}
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
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{
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/*
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* Check for any power failure to determine if this a wake from
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* S5 because the PCH does not set the WAK_STS bit when waking
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* from a true G3 state.
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*/
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if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
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prev_sleep_state = ACPI_S5;
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/*
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* If waking from S3 determine if deep S3 is enabled. If not,
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* need to check both deep sleep well and normal suspend well.
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* Otherwise just check deep sleep well.
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*/
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if (prev_sleep_state == ACPI_S3) {
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/* PWR_FLR represents deep sleep power well loss. */
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uint32_t mask = PWR_FLR;
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/* If deep s3 isn't enabled check the suspend well too. */
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if (!deep_s3_enabled())
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mask |= SUS_PWR_FLR;
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if (ps->gen_pmcon_a & mask)
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prev_sleep_state = ACPI_S5;
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}
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return prev_sleep_state;
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}
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint8_t *pmc;
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ps->tco1_sts = tco_read_reg(TCO1_STS);
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ps->tco2_sts = tco_read_reg(TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
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pmc = pmc_mmio_regs();
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ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
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ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
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ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
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ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
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ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
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printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
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ps->gen_pmcon_a, ps->gen_pmcon_b);
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printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
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ps->gblrst_cause[0], ps->gblrst_cause[1]);
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printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
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}
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/* STM Support */
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uint16_t get_pmbase(void)
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{
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return (uint16_t)ACPI_BASE_ADDRESS;
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}
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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*/
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void pmc_soc_set_afterg3_en(const bool on)
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{
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uint8_t reg8;
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uint8_t *const pmcbase = pmc_mmio_regs();
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reg8 = read8(pmcbase + GEN_PMCON_A);
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if (on)
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reg8 &= ~SLEEP_AFTER_POWER_FAIL;
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else
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reg8 |= SLEEP_AFTER_POWER_FAIL;
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write8(pmcbase + GEN_PMCON_A, reg8);
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}
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