soc/intel/tigerlake: Switch to common global reset implementation

Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.

Changes:
- Remove src/soc/intel/tigerlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build

The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.

Change-Id: I1bf9d4eeab0fecbb33d122a32ecdeef85af059fa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>

src/soc/intel/tigerlake/Kconfig

@@ -74,6 +74,7 @@ config SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
+	select SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE

src/soc/intel/tigerlake/Makefile.mk

@@ -15,7 +15,6 @@ bootblock-y += p2sb.c
 
 romstage-y += meminit.c
 romstage-y += pcie_rp.c
-romstage-y += reset.c
 
 ramstage-y += acpi.c
 ramstage-y += chip.c
@@ -29,7 +28,6 @@ ramstage-y += lpm.c
 ramstage-y += p2sb.c
 ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
-ramstage-y += reset.c
 ramstage-y += retimer.c
 ramstage-y += systemagent.c
 ramstage-y += tcss.c

src/soc/intel/tigerlake/reset.c

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cf9_reset.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
-#include <soc/intel/common/reset.h>
-
-void do_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (cse_request_global_reset() == CSE_TX_RX_SUCCESS)
-		return;
-
-	/* global reset if CSE fail to reset */
-	pmc_global_reset_enable(1);
-	do_full_reset();
-}