soc/intel/common/feature: Add common PMC lockdown driver

This commit introduces common PMC (Power Management Controller) lockdown
infrastructure to consolidate duplicate lockdown code across multiple
Intel platform generations (Alder Lake, Meteor Lake, and Panther Lake).

Key features implemented:
- PMSYNC TPR configuration and locking
- ABASE and sleep stretching policy locks
- SMI locking (when coreboot handles chipset lockdown)
- ST_FDIS_LOCK, SSML, and PM_CFG register configuration
- IOSF Primary Trunk Clock Gating
- PMC IPC notification for BIOS reset and PCI enumeration

Platform-specific differences are handled through the PMC_FDIS_LOCK_REG
define that each SoC provides in its soc/pmc.h header:
- Alder Lake: PMC_FDIS_LOCK_REG = ST_PG_FDIS1 (0x1e20)
- Meteor Lake: PMC_FDIS_LOCK_REG = GEN_PMCON_B (0x1024)
- Panther Lake: PMC_FDIS_LOCK_REG = GEN_PMCON_B (0x1024)

This consolidation eliminates ~150 lines of duplicated code, ensures
consistent lockdown behavior across platforms, and simplifies
maintenance.

Change-Id: I215d834b66f7cb0f50f804eaaff3ea0e60d4340f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91204
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/feature/lockdown/Kconfig

@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_INTEL_COMMON_FEATURE_LOCKDOWN
+	bool
+	help
+	  Include common PMC lockdown driver for Intel SoCs. This driver
+	  consolidates the nearly identical PMC lockdown implementations
+	  across multiple Intel platform generations.

src/soc/intel/common/feature/lockdown/Makefile.mk

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_FEATURE_LOCKDOWN) += lockdown.c

src/soc/intel/common/feature/lockdown/lockdown.c

@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+#include <stdint.h>
+
+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG		0x1d00
+#define PSTH_CTRLREG_IOSFPTCGE		BIT(2)
+
+static void pmc_lockdown_config(int chipset_lockdown)
+{
+	uint8_t *pmcbase = pmc_mmio_regs();
+
+	/* PMSYNC */
+	setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
+	/* Lock down ABASE and sleep stretching policy */
+	setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+
+	if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
+		setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
+		setbits32(pmcbase + PMC_FDIS_LOCK_REG, ST_FDIS_LOCK);
+		setbits32(pmcbase + SSML, SSML_SSL_EN);
+		setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
+					 PM_CFG_XRAM_READ_DISABLE);
+	}
+
+	/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
+	pmc_send_bios_reset_pci_enum_done();
+}
+
+static void soc_die_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+	/* PMC lock down configuration */
+	pmc_lockdown_config(chipset_lockdown);
+	/* SOC/PCH die lock down configuration */
+	soc_die_lockdown_cfg();
+}