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soc/intel/meteorlake: Switch to common PMC lockdown driver

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Replace platform-specific lockdown.c with the common PMC lockdown
driver.

Changes:
- Remove src/soc/intel/meteorlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build

Meteor Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Panther Lake.

Change-Id: Iecccc482f04d85cfec738dd57dc1473eaf82cfcc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This commit is contained in:
Jeremy Compostella 2026-02-13 23:35:41 -08:00 • committed by Jérémy Compostella
commit 4da2622964
4 changed files with 4 additions and 55 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/soc/intel/meteorlake/Kconfig
View file

@ -89,6 +89,7 @@ config SOC_INTEL_METEORLAKE
select SOC_INTEL_COMMON_FEATURE
select SOC_INTEL_COMMON_FEATURE_ESPI
select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_LOCKDOWN
select SOC_INTEL_COMMON_FEATURE_PMUTIL
select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE

1
src/soc/intel/meteorlake/Makefile.mk
View file

@ -29,7 +29,6 @@ ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
ramstage-y += pcie_rp.c
ramstage-y += pmc.c

3
src/soc/intel/meteorlake/include/soc/pmc.h
View file

@ -62,6 +62,9 @@ extern struct device_operations ioe_pmc_ops;
#define SMI_LOCK (1 << 4)
#define RTC_BATTERY_DEAD (1 << 2)
/* PMC lockdown configuration register for ST_FDIS_LOCK */
#define PMC_FDIS_LOCK_REG GEN_PMCON_B
#define ETR 0x1048
#define CF9_LOCK (1 << 31)
#define CF9_GLB_RST (1 << 20)

54
src/soc/intel/meteorlake/lockdown.c
View file

@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <intelblocks/cfg.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelpch/lockdown.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <stdint.h>
/* PCR PSTH Control Register */
#define PCR_PSTH_CTRLREG 0x1d00
#define PSTH_CTRLREG_IOSFPTCGE (1 << 2)
static void pmc_lockdown_cfg(int chipset_lockdown)
{
uint8_t *pmcbase = pmc_mmio_regs();
/* PMSYNC */
setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
/* Lock down ABASE and sleep stretching policy */
setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK);
setbits32(pmcbase + SSML, SSML_SSL_EN);
setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
PM_CFG_XRAM_READ_DISABLE);
}
/* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
pmc_send_bios_reset_pci_enum_done();
}
static void soc_die_lockdown_cfg(void)
{
if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
return;
/* Enable IOSF Primary Trunk Clock Gating */
pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
}
void soc_lockdown_config(int chipset_lockdown)
{
/* PMC lock down configuration */
pmc_lockdown_cfg(chipset_lockdown);
/* SOC Die lock down configuration */
soc_die_lockdown_cfg();
}