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soc/qualcomm/x1p42100: Remove redundant VBUS enablement logic

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The current VBUS enablement logic was found to be unnecessary for
USB host functionality on x1p42100. Forcing VBUS power via the PMIC's
OTG buck is not required for the current hardware configuration and
could lead to incorrect power state management.

Remove the enable_vbus_ss() function and associated SCHG DCDC
register definitions from the SoC driver. This streamlines the
USB initialization path to focus solely on PHY and controller
setup.

TEST=Verify USB detection in the depthcharge on Google/Quartz.

Change-Id: Ie30878802831419f3d70ea921f7f46a262db99bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2026-03-02 12:10:51 +05:30 • committed by Subrata Banik
commit c222118cbf
2 changed files with 0 additions and 66 deletions
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14
src/soc/qualcomm/x1p42100/include/soc/usb/usb.h
View file

@ -103,25 +103,13 @@
#define SMB2_SLAVE_ID 0x0A
/* SCHG DCDC register offsets */
#define SCHG_DCDC_CMD_OTG 0x2740
#define SCHG_DCDC_OTG_CFG 0x2753
#define SCHG_DCDC_OTG_STATUS 0x270D
#define SCHG_DCDC_ENG_SDCDC_CFG7 0x27C7
#define SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK 0x30
/* OTG Status register bit definitions */
#define OTG_STATE_MASK 0x07
#define OTG_STATE_ENABLED 0x02
#define OTG_STATUS_TIMEOUT_MS 20
#define OTG_STATUS_POLL_DELAY_MS 2
#define OTG_BUCK_CFG 0x26
/* Type-C register offsets */
#define SCHG_TYPE_C_TYPE_C_MISC_STATUS 0x2B0B
#define SCHG_TYPE_C_TYPE_C_SRC_STATUS 0x2B08
#define SCHG_TYPE_C_TYPE_C_MODE_CFG 0x2B44
#define TYPEC_VBUS_STATUS_MASK BIT(5)
#define TYPEC_SNK_SRC_MODE BIT(6)
#define CCOUT_INVERT_POLARITY 0x03
/* USB Repeater SPMI Tune register offsets */
@ -152,8 +140,6 @@ int qcom_enable_usb_clk(void);
void enable_clock_tcsr(void);
/* Enable TCSR CLKREF */
void usb_update_refclk_for_core(u32 core_num, bool enable);
/* Enables VBUS SuperSpeed for specified USB core */
void enable_vbus_ss(const struct dwc3_controller_config *config);
/* Reads comprehensive Type-C status from PMIC */
void usb_typec_status_check(const struct dwc3_controller_config *config);
/* Performs mainboard-specific USB Type-C configuration */

52
src/soc/qualcomm/x1p42100/usb/usb.c
View file

@ -598,9 +598,6 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
}
/* Configure OTG buck */
usb_configure_otg_buck(&prim_config);
/* Enable VBUS for C0 */
enable_vbus_ss(&prim_config);
udelay(50);
usb_typec_status_check(&prim_config);
mainboard_usb_typec_configure(0, polarity_prim);
@ -631,9 +628,6 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3)
}
/* Configure OTG buck */
usb_configure_otg_buck(&sec_config);
/* Enable VBUS for C1 */
enable_vbus_ss(&sec_config);
udelay(50);
usb_typec_status_check(&sec_config);
mainboard_usb_typec_configure(1, polarity_sec);
@ -685,52 +679,6 @@ void usb_update_refclk_for_core(u32 core_num, bool enable)
}
}
/*
* enable_vbus_ss - Enables VBUS SuperSpeed for specified USB core
* @config: Controller configuration containing SMB slave address
*/
void enable_vbus_ss(const struct dwc3_controller_config *config)
{
u8 slave = config->smb_slave_addr;
u8 misc_status, otg_status = 0, otg_state = 0;
struct stopwatch sw;
printk(BIOS_INFO, "Enabling %s VBUS SuperSpeed\n", config->name);
/* Configure SDCDC CFG7 register before enabling OTG */
spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_ENG_SDCDC_CFG7),
SCHG_DCDC_ENG_SDCDC_GM_CLOOP_PD_OTG_BUCK_MASK);
spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_OTG_CFG), 0x20);
spmi_write8(SPMI_ADDR(slave, SCHG_DCDC_CMD_OTG), 0x1);
/* Check Type-C mode */
misc_status = spmi_read8(SPMI_ADDR(slave, SCHG_TYPE_C_TYPE_C_MISC_STATUS));
/* Check SNK_SRC_MODE bit (bit 6): 0 = SNK, 1 = SRC */
if (misc_status & TYPEC_SNK_SRC_MODE) {
/* In SRC mode, poll OTG status until enabled */
stopwatch_init_msecs_expire(&sw, OTG_STATUS_TIMEOUT_MS);
while (!stopwatch_expired(&sw)) {
otg_status = spmi_read8(SPMI_ADDR(slave, SCHG_DCDC_OTG_STATUS));
otg_state = otg_status & OTG_STATE_MASK;
if (otg_state == OTG_STATE_ENABLED) {
printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x (OTG Enabled)\n",
config->name, otg_status, otg_state);
return;
}
mdelay(OTG_STATUS_POLL_DELAY_MS);
}
/* Timeout - log final state */
printk(BIOS_INFO, "%s in SRC mode - OTG Status: 0x%02x, State: 0x%02x - Timeout after %d ms\n",
config->name, otg_status, otg_state, OTG_STATUS_TIMEOUT_MS);
} else {
printk(BIOS_INFO, "%s in SNK mode - skipping OTG status read\n", config->name);
}
}
/*
* usb_typec_status_check - Reads comprehensive Type-C status from PMIC
* @config: Controller configuration containing SMB slave address