soc/intel/tigerlake: Use common PCH client SMI handler
Migrate Tiger Lake to use the common PCH client SMI handler implementation from the Intel common feature code. This change eliminates platform-specific code by leveraging the shared smihandler.c driver. This commit: - Adds SOC_PMC_DEV macro definition to soc/pci_devs.h - Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig - Removes src/soc/intel/tigerlake/smihandler.c - Updates Makefile to remove smihandler.c compilation Tiger Lake uses PCH_DEV_PMC as the PMC device identifier. Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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4 changed files with 2 additions and 31 deletions
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@ -75,6 +75,7 @@ config SOC_INTEL_TIGERLAKE
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select SOC_INTEL_COMMON_FEATURE
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select SOC_INTEL_COMMON_FEATURE_ESPI
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select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
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select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
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select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
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select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
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select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
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@ -38,7 +38,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += elog.c
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smm-y += xhci.c
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@ -250,6 +250,7 @@
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#define PCI_DEVFN_UART1 PCH_DEVFN_UART1
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#define PCI_DEVFN_UART2 PCH_DEVFN_UART2
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#define SOC_GSPI_DEVFN(n) PCH_DEVFN_GSPI##n
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#define SOC_PMC_DEV PCH_DEV_PMC
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#endif
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@ -1,30 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_def.h>
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#include <intelblocks/smihandler.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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int smihandler_soc_disable_busmaster(pci_devfn_t dev)
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{
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/* Skip disabling PMC bus master to keep IO decode enabled */
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if (dev == PCH_DEV_PMC)
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return 0;
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return 1;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
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[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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[MCSMI_STS_BIT] = smihandler_southbridge_mc,
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
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[TCO_STS_BIT] = smihandler_southbridge_tco,
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#endif
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[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
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};
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