soc/intel/tigerlake: Use common PCH client SMI handler

Migrate Tiger Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.

This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/tigerlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation

Tiger Lake uses PCH_DEV_PMC as the PMC device identifier.

Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2026-02-26 10:48:14 -08:00 committed by Matt DeVillier
commit d03957e10f
4 changed files with 2 additions and 31 deletions

View file

@ -75,6 +75,7 @@ config SOC_INTEL_TIGERLAKE
select SOC_INTEL_COMMON_FEATURE
select SOC_INTEL_COMMON_FEATURE_ESPI
select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF

View file

@ -38,7 +38,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += elog.c
smm-y += xhci.c

View file

@ -250,6 +250,7 @@
#define PCI_DEVFN_UART1 PCH_DEVFN_UART1
#define PCI_DEVFN_UART2 PCH_DEVFN_UART2
#define SOC_GSPI_DEVFN(n) PCH_DEVFN_GSPI##n
#define SOC_PMC_DEV PCH_DEV_PMC
#endif

View file

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_def.h>
#include <intelblocks/smihandler.h>
#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
int smihandler_soc_disable_busmaster(pci_devfn_t dev)
{
/* Skip disabling PMC bus master to keep IO decode enabled */
if (dev == PCH_DEV_PMC)
return 0;
return 1;
}
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
[GPIO_STS_BIT] = smihandler_southbridge_gpi,
[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
[MCSMI_STS_BIT] = smihandler_southbridge_mc,
#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
[TCO_STS_BIT] = smihandler_southbridge_tco,
#endif
[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
};