Program initial memory controller settings. Many of these values will be
adjusted later during training.
Change-Id: If33846b51cb1bab5d0458fe626e13afb1bdc900e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64186
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.
Specifically, it:
- Moves Kconfig options related to low-battery notifications from
drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Controller2 and controller3 are disabled, so remove them from source
code.
BRANCH=rauru
BUG=b:389026545
TEST=Boot up to kernel
Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit renames the cbmem ID from CBMEM_ID_FSP_LOGO to
CBMEM_ID_BMP_LOGO.
This change:
- Standardizes the naming to reflect the actual content, which is a
BMP logo.
- Removes the FSP-specific prefix, making the ID more generic and
suitable for use in the common library.
- Aligns the code with the recent Kconfig changes that moved BMP_LOGO
related options to the common library.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I838d4e6ad0efdef063f2cc78bb83d1d37e065f45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit relocates the BMP_LOGO related Kconfig options from the
FSP1.1 and FSP2.0 drivers to the common library (lib/).
This change:
- Centralizes the BMP_LOGO configuration, making it accessible to
all drivers and platforms.
- Removes duplicate Kconfig entries from the FSP drivers.
- Prepares for future refactoring where BMP_LOGO will be handled
entirely within the library, enabling its use by both FSP and
non-FSP platforms.
The following Kconfig options are moved under "Boot Logo Configuration"
menu option:
- `BMP_LOGO`
- `BMP_LOGO_COMPRESS_LZMA`
- `BMP_LOGO_COMPRESS_LZ4`
- `BMP_LOGO_FILE_NAME`
- `HAVE_BMP_LOGO_COMPRESS_LZMA`
- `HAVE_CUSTOM_BMP_LOGO`
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I9bbfade9b919cfbd0b689a67c988ed8c65deb597
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86730
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit standardizes the Kconfig option for the boot logo file name
across FSP drivers and the common library.
The `FSP1_1_LOGO_FILE_NAME` and `FSP2_0_LOGO_FILE_NAME` options are
renamed to `BMP_LOGO_FILE_NAME`.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I6a6c2c6d235ad9643879b00232930c8a0d2e3801
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change eliminates the HAVE_FSP_LOGO_SUPPORT Kconfig option.
It was initially used to control BMP_LOGO selection within the FSP2.0
driver. However, upcoming refactoring will move BMP_LOGO and its
implementation to the `lib` directory therefore, BMP_LOGO can be
used by both FSP and non-FSP SoC platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: I899bbfcf7e747abe69ff0866c4594a42278891b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86719
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Both USB Type-C ports do not have retimers, so configure this
accordingly.
Change-Id: I341e54984b768ff5b1020c6d127b0c4b18b8725c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a simply macro to make the value set for tcc_offset easier to
read.
Then, unify the settings across all boards:
* 70, 80 and 90 degrees for fanless boards
* 80, 90 and 100 degrees for fanned boards
Change-Id: I5c0323aea0d9d3b09e60f88c3a95c821ab1d3b7d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86740
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards configure pch_thermal_trip based on the performance
profile, and some set tcc_offset.
tcc_offset makes more sense here, so change all the boards to be
the same.
Change-Id: Id55b5d971c895baa1ba97137351fbd0aea3317d8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86728
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the MSG0 method to the ACP's SSDT entry, so that the ACP driver can
talk to a two different mailbox interfaces via this ACPI MSG0 method
interface. This is used by some drivers to configure the ACP's clock
source and to notify the PSP that the audio DSP firmware has been loaded
so that the PSP can validate the firmware and set the qualifier bit to
enable running it.
TEST=The AML code sequence written by this decompiles to the expected
ASL code and the driver is able to initialize the ACP correctly by
calling the MSG0 method twice with different parameters.
Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two ACPI methods to access a PSP mailbox interface via an SMN
register pair in the host bridge.
TEST=The AML code sequence written by this decompiles to the expected
ASL code.
Change-Id: I282f1fa2898f76659700450ee1f4b11f79d2d030
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SoCs require adding SoC-specific methods to the ACP's SSDT entry.
In order to not add SoC-specific code to the common ACP code, add the
'acp_soc_write_ssdt_entry' callback into the SoC-specific code and guard
it via the 'SOC_AMD_COMMON_BLOCK_ACP_SOC_SPECIFIC_SSDT_ENTRY' Kconfig
symbol to neither need weak functions or stubs in every SoC code.
Change-Id: I0ca5272d28938c8b90b645884a0d8b306a77d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add an ACPI OperationRegion to access an SMN access index/data register
pair in the root complex. To access the PCI config space registers, the
ECAM MMCONF MMIO region is used which matches the UEFI reference
implementation.
TEST=The AML code sequence written by this decompiles to the expected
ASL code.
Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, the 'acpigen_write_byte_buffer' function required both the
byte buffer length and the initialization data byte array 'arr'. The
ACPI spec however allows buffer declarations with only the length, but
without an initialization data byte array. In this case the AML
interpreter will create a buffer of the given length with all bytes
initialized to 0x00. In order to not need another function, allow the
'arr' parameter for the pointer to the initialization data byte array to
be NULL and in that case don't write the optional buffer initialization
byte array.
TEST=Calling 'acpigen_write_byte_buffer' with 'NULL' as first parameter
results in the AML code sequence being written which decompiles to ASL
as expected.
Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86631
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement functions to write the AML bytes corresponding to
CreateBitField for both OP buffers and named buffers.
TEST=Calling 'acpigen_write_create_buffer_bit_field' results in the AML
code sequence being written which decompiles to ASL as expected.
Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement functions to write the AML bytes corresponding to
'If (LNotEqual (...))' which is equivalent to 'If (LNot (LEqual (...)))'
for the value types combinations 2 OPs, OP and value, and namestring and
value.
TEST=Calling 'acpigen_write_if_lnotequal_op_int' results in the AML code
sequence being written which decompiles to ASL as expected.
Change-Id: I6c664bc4d30a49ae990eeb9f0e0776cac37efc57
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The system default VSP/VSN voltage for Ciri is +-5.7V, which causes
the Gray screen pattern to display abnormally with screen corruption.
According to CSOT panel vendor's requirement, VSP/VSN for the
CSOT_PNA957QT1_1 panel needs to be adjusted to +-6V. So modify the
relevant register values accordingly.
BUG=b:399728328
TEST=Boot to firmware screen and kernel, measure the voltage.
BRANCH=geralt
Change-Id: I1b69303317f5ef47818f4a6a0c851bf650285e51
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86640
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
IOT FSP binaries for MTL are available on github, so add FSP_TYPE_IOT
Kconfig option, select 'HAVE_INTEL_FSP_REPO', and add the paths for the
FSP headers and binary.
TEST=build/boot starlabs/starbook_mtl
Change-Id: I44ee923f4d1151f0e11104af7db53ce59551cf37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86611
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This is just a copy of fatcat at the moment.
BUG=b:372502513
TEST=Build AP firmware image.
Change-Id: Iee93610f3367f4c850b4fcc8827a4a4d44b46117
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86692
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on constitution device and verify that
the device suspends to S0ix.
Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86686
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on brya device and verify that the device
suspends to S0ix.
Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86685
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on nova and verify that the device
suspends to S0ix.
Change-Id: Icb36285d0a12dcb098282b08ef794256af67b019
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86649
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on gladios and verify that the device
suspends to S0ix.
Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86648
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on gaelin and verify that the device
suspends to S0ix.
Change-Id: I4a3f4fbddae3806f548705e9a492379c0b38a415
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on vell and verify that the device
suspends to S0ix.
Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86646
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
All AMD SoCs from family 17h on, so all using a non-CAR configuration
to boot, have a reference clock of 100 MHz, so report this for all of
them in the SMBIOS tables.
Change-Id: I9573cbb8ec816c797314415d0c60c72abf23a094
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86690
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit fe107c1ad2.
I have strong doubts that this is Glinda-specific, so this likely should
have been made common after verifying.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib7282e2bec4d6aa5b74efa5621c825bc234cca82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86689
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 00b4a61dc5.
I have strong doubts that this is Glinda-specific, so this probably
should have been made common after verifying.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7fa0dca4c92f7bb0d49956aa9f1588b5fcba585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86688
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Update VBT to fix HDMI
- Enable ITE environment controller
- Enable PTT fTPM
- Disable s0ix, it never worked and will crash if used
- Set CLKREQ# based on register values from vendor firmware
- Set pmc_gpe0_dw{0-3} to fix "Duplicate GPE DW register values"
Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716
Signed-off-by: Brandon Weeks <bweeks@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
pch_is_lp() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.
Change-Id: Ic7bf801f549077cbd493e0a53ba7eff7a72728fb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A glinda based platform reports:
[WARN] RAM APOB data is too large (3b3b0 + 8) > 1e000
APOB NV size is not enough on recent platforms to cache memory training,
which causes the same amount of boot time on subsequent boots as on the
first boot.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8cc1f1e4f8d6f99c8e2b717926b66a5a683bffdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
haswell_is_ult() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.
Change-Id: I3c98ee819fc937ed6da9ee1340c2af10cec19eb3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
As mentioned in comments on CB:83422, size of the current data
block (which is also the last block of a capsule) was incorrectly used
in place of the capsule size:
- when publishing a capsule in CBMEM (this worked in practice because
CapsuleApp.efi allocates a continuous physical memory)
- when aligning target address (which could move output pointer past
previously allocated buffer by up to 7 bytes per capsule block)
Change-Id: I97a528e2611fcd711c555d0f01e9aadcd2031217
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84542
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO is used for clock request 5, which is NF2.
Change-Id: Ic5712090339a39a269aa1aefca9f54da11cb6528
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86654
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These were incorrectly copied from Alder Lake so remove them
as they are not correct nor needed.
Change-Id: I70708212c4652ed77c875242340c30edf5b935a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86651
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.
BUG=b:391612392
TEST=Run suspend_stress_test on lisbon and verify that the device
suspends to S0ix.
Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.
BUG=b:391612392
TEST=Run suspend_stress_test on Bujia and verify that the device
suspends to S0ix.
Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GPP_H08 and GPP_H09 are configured in the bootblock, so remove the
configuration in ramstage to allow the serial output in ramstage.
Change-Id: I4b813370cf259fb1ca138dd1922c16f801b40cc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Generate a new TME key will cause S3 exit to fail, so
don't do it.
Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
