mb/google/ocelot: Create Ocelot board
This is just a copy of fatcat at the moment. BUG=b:372502513 TEST=Build AP firmware image. Change-Id: Iee93610f3367f4c850b4fcc8827a4a4d44b46117 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86692 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal
Subrata Banik
parent
7eb53f8623
commit
c4afd04547
32 changed files with 3081 additions and 0 deletions
143
src/mainboard/google/ocelot/Kconfig
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143
src/mainboard/google/ocelot/Kconfig
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_GOOGLE_OCELOT_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select CPU_INTEL_SOCKET_OTHER
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select DRIVERS_GFX_GENERIC
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_WWAN_FM350GL
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select DRIVERS_AUDIO_SOF
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select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
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select DRIVERS_SPI_ACPI
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select DUMP_SMBIOS_TYPE17
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select EC_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_SKUID
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select FW_CONFIG
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select FW_CONFIG_SOURCE_CHROMEEC_CBI
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select GENERATE_SMBIOS_TABLES
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select I2C_TPM
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_DISABLE_STAGE_CACHE
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select MAINBOARD_HAS_TPM2
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select MB_COMPRESS_RAMSTAGE_LZ4
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
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select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
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select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
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select SOC_INTEL_WILDCATLAKE
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select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
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config BOARD_GOOGLE_BASEBOARD_OCELOT
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def_bool n
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select BOARD_GOOGLE_OCELOT_COMMON
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_INTEL_ISH
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select DRIVER_INTEL_ISH_HAS_MAIN_FW
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select DRIVERS_INTEL_USB4_RETIMER
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select HAVE_SLP_S0_GATE
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select MAINBOARD_HAS_CHROMEOS
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_IOE_DIE_SUPPORT
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SYSTEM_TYPE_LAPTOP
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select TPM_GOOGLE_TI50
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config BOARD_GOOGLE_OCELOT
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select BOARD_GOOGLE_BASEBOARD_OCELOT
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_MAX98357A
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select EC_GOOGLE_CHROMEEC_MEC
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_WILDCATLAKE
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if BOARD_GOOGLE_OCELOT_COMMON
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config BASEBOARD_DIR
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string
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default "ocelot"
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select HAS_RECOVERY_MRC_CACHE
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config CHROMEOS_WIFI_SAR
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bool "Enable SAR options for ChromeOS build"
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depends on CHROMEOS
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select DSAR_ENABLE
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select GEO_SAR_ENABLE
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select SAR_ENABLE
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select USE_SAR
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config DEVICETREE
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default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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default 512
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x03 if BOARD_GOOGLE_OCELOT
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config HAVE_SLP_S0_GATE
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def_bool n
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config MAINBOARD_DIR
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default "google/ocelot"
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config MAINBOARD_FAMILY
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string
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default "Google_Ocelot"
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# FIXME: update once Ocelot config is available
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config MAINBOARD_PART_NUMBER
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default "Fatcat" if BOARD_GOOGLE_OCELOT
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config MEMORY_SOLDERDOWN
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def_bool n
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select HAVE_SPD_IN_CBFS
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 47 if BOARD_GOOGLE_OCELOT # GPE0_DW1_15 (GPP_D15)
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# FIXME: update as per board schematics
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config UART_FOR_CONSOLE
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int
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default 0
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config USE_PM_ACPI_TIMER
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default n
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config VARIANT_DIR
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string
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default "ocelot" if BOARD_GOOGLE_OCELOT
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config VBOOT
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select VBOOT_LID_SWITCH
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endif # BOARD_GOOGLE_OCELOT_COMMON
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6
src/mainboard/google/ocelot/Kconfig.name
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6
src/mainboard/google/ocelot/Kconfig.name
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-only
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comment "Ocelot"
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config BOARD_GOOGLE_OCELOT
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bool "-> Ocelot"
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26
src/mainboard/google/ocelot/Makefile.mk
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26
src/mainboard/google/ocelot/Makefile.mk
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@ -0,0 +1,26 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += variants/$(VARIANT_DIR)/hda_verb.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
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subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
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subdirs-y += variants/$(VARIANT_DIR)
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subdirs-y += variants/$(VARIANT_DIR)/memory
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subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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6
src/mainboard/google/ocelot/board_info.txt
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6
src/mainboard/google/ocelot/board_info.txt
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Vendor name: Google
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Board name: Ocelot
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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13
src/mainboard/google/ocelot/bootblock.c
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13
src/mainboard/google/ocelot/bootblock.c
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_early_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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34
src/mainboard/google/ocelot/chromeos.c
Normal file
34
src/mainboard/google/ocelot/chromeos.c
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <types.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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#if CONFIG(VBOOT_LID_SWITCH)
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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#else
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/* fake LID open to avoid shutdown in depthcharge */
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{-1, ACTIVE_HIGH, 1, "lid"},
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#endif
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_write_protect_state(void)
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{
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return gpio_get(GPIO_PCH_WP);
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}
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int get_ec_is_trusted(void)
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{
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/* VB2_CONTEXT_EC_TRUSTED should be set according to the Ti50 boot mode. */
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return 0;
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}
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49
src/mainboard/google/ocelot/chromeos.fmd
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49
src/mainboard/google/ocelot/chromeos.fmd
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FLASH 32M {
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SI_ALL 8M {
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SI_DESC 16K
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SI_ME
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}
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SI_BIOS 24M {
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RW_SECTION_A 8M {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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}
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# This section starts at the 16M boundary in SPI flash.
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# PTL does not support a region crossing this boundary,
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# because the SPI flash is memory-mapped into two non-
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# contiguous windows.
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RW_SECTION_B 8M {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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}
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RW_MISC 1M {
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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RW_ELOG(PRESERVE) 16K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 24K
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}
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RW_LEGACY(CBFS) 1M
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RW_UNUSED 2M
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 4M {
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RO_VPD(PRESERVE) 16K
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RO_GSCVD 8K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 12K
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COREBOOT(CBFS)
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}
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}
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}
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}
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42
src/mainboard/google/ocelot/dsdt.asl
Normal file
42
src/mainboard/google/ocelot/dsdt.asl
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20240917
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/pantherlake/acpi/southbridge.asl>
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#include <soc/intel/pantherlake/acpi/tcss.asl>
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}
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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22
src/mainboard/google/ocelot/ec.c
Normal file
22
src/mainboard/google/ocelot/ec.c
Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <console/console.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <variant/ec.h>
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void mainboard_ec_init(void)
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{
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static const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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printk(BIOS_DEBUG, "mainboard: EC init\n");
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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74
src/mainboard/google/ocelot/mainboard.c
Normal file
74
src/mainboard/google/ocelot/mainboard.c
Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <ec/ec.h>
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#include <soc/ramstage.h>
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#include <stdlib.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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/* default implementation does nothing */
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}
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void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
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{
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variant_update_soc_chip_config(config);
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}
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void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
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{
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/* default implementation does nothing */
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}
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static void mainboard_init(void *chip_info)
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{
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struct pad_config *padbased_table;
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const struct pad_config *base_pads;
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size_t base_num;
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padbased_table = new_padbased_table();
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base_pads = variant_gpio_table(&base_num);
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gpio_padbased_override(padbased_table, base_pads, base_num);
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fw_config_gpio_padbased_override(padbased_table);
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gpio_configure_pads_with_padbased(padbased_table);
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free(padbased_table);
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baseboard_devtree_update();
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}
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void __weak baseboard_devtree_update(void)
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{
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/* Override dev tree settings per baseboard */
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}
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void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
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{
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/* Add board-specific MS0X entries */
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/*
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if (s0ix_entry == S0IX_ENTRY) {
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implement variant operations here
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}
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if (s0ix_entry == S0IX_EXIT) {
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implement variant operations here
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}
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*/
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}
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static void mainboard_dev_init(struct device *dev)
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{
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mainboard_ec_init();
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_dev_init;
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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36
src/mainboard/google/ocelot/romstage.c
Normal file
36
src/mainboard/google/ocelot/romstage.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <fsp/api.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
|
||||
/*
|
||||
* Placeholder to configure GPIO early from romstage relying on the FW_CONFIG.
|
||||
*
|
||||
* If any platform would like to override early GPIOs, they should override from
|
||||
* the variant directory.
|
||||
*/
|
||||
__weak void fw_config_configure_pre_mem_gpio(void)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
const struct pad_config *pads;
|
||||
size_t pads_num;
|
||||
const struct mb_cfg *mem_config = variant_memory_params();
|
||||
bool half_populated = variant_is_half_populated();
|
||||
struct mem_spd spd_info;
|
||||
|
||||
pads = variant_romstage_gpio_table(&pads_num);
|
||||
if (pads_num)
|
||||
gpio_configure_pads(pads, pads_num);
|
||||
fw_config_configure_pre_mem_gpio();
|
||||
|
||||
memset(&spd_info, 0, sizeof(spd_info));
|
||||
variant_get_spd_info(&spd_info);
|
||||
|
||||
memcfg_init(memupd, mem_config, &spd_info, half_populated);
|
||||
}
|
||||
29
src/mainboard/google/ocelot/smihandler.c
Normal file
29
src/mainboard/google/ocelot/smihandler.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <ec/google/chromeec/smm.h>
|
||||
#include <elog.h>
|
||||
#include <intelblocks/smihandler.h>
|
||||
#include <variant/ec.h>
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void elog_gsmi_cb_mainboard_log_wake_source(void)
|
||||
{
|
||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS);
|
||||
}
|
||||
|
||||
void mainboard_smi_espi_handler(void)
|
||||
{
|
||||
chromeec_smi_process_events();
|
||||
}
|
||||
6
src/mainboard/google/ocelot/spd/Makefile.mk
Normal file
6
src/mainboard/google/ocelot/spd/Makefile.mk
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
##
|
||||
|
||||
ifneq ($(SPD_SOURCES),)
|
||||
LIB_SPD_DEPS := $(SPD_SOURCES)
|
||||
endif
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_VARIANTS_H__
|
||||
#define __BASEBOARD_VARIANTS_H__
|
||||
|
||||
#include <chip.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of entries for
|
||||
* each table.
|
||||
*/
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num);
|
||||
void fw_config_configure_pre_mem_gpio(void);
|
||||
void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void);
|
||||
void variant_get_spd_info(struct mem_spd *spd_info);
|
||||
int variant_memory_sku(void);
|
||||
bool variant_is_half_populated(void);
|
||||
void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
|
||||
|
||||
enum s0ix_entry {
|
||||
S0IX_EXIT,
|
||||
S0IX_ENTRY,
|
||||
};
|
||||
|
||||
void variant_generate_s0ix_hook(enum s0ix_entry entry);
|
||||
|
||||
/* Modify devictree settings during ramstage by baseboard */
|
||||
void baseboard_devtree_update(void);
|
||||
/* Modify devictree settings during ramstage by dedicated variant */
|
||||
void variant_devtree_update(void);
|
||||
|
||||
#endif /*__BASEBOARD_VARIANTS_H__ */
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
romstage-y += memory.c
|
||||
ramstage-y += ramstage.c
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
chip soc/intel/pantherlake
|
||||
# GPE configuration
|
||||
register "pmc_gpe0_dw0" = "GPP_A"
|
||||
register "pmc_gpe0_dw1" = "GPP_D"
|
||||
register "pmc_gpe0_dw2" = "GPP_E"
|
||||
|
||||
# For Ocelot variants with microchip EC:
|
||||
# EC host command ranges are in 0x800-0x807 & 0x200-0x20f
|
||||
# For Ocelot variants with ITE/Nuvoton EC:
|
||||
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
|
||||
register "gen1_dec" = "CONFIG(BOARD_GOOGLE_OCELOT)? 0x00040801 : 0x00fc0801"
|
||||
register "gen2_dec" = "0x000c0201"
|
||||
# EC memory map range is 0x900-0x9ff
|
||||
register "gen3_dec" = "0x00fc0901"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
|
||||
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
|
||||
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
|
||||
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
|
||||
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
|
||||
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
|
||||
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
|
||||
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
|
||||
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
|
||||
register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
|
||||
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
|
||||
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
|
||||
|
||||
# Enable SAGv
|
||||
register "sagv" = "SAGV_ENABLED"
|
||||
|
||||
register "sagv_freq_mhz[0]" = "2400"
|
||||
register "sagv_gear[0]" = "GEAR_4"
|
||||
|
||||
register "sagv_freq_mhz[1]" = "3200"
|
||||
register "sagv_gear[1]" = "GEAR_4"
|
||||
|
||||
register "sagv_freq_mhz[2]" = "6000"
|
||||
register "sagv_gear[2]" = "GEAR_4"
|
||||
|
||||
register "sagv_freq_mhz[3]" = "6400"
|
||||
register "sagv_gear[3]" = "GEAR_4"
|
||||
|
||||
# Enable s0ix
|
||||
register "s0ix_enable" = "true"
|
||||
|
||||
# DPTF enable
|
||||
register "dptf_enable" = "true"
|
||||
|
||||
# Setting TCC of 100C = Tj max (110) - TCC_Offset (10)
|
||||
register "tcc_offset" = "10"
|
||||
|
||||
# Disable C1 C-state auto-demotion
|
||||
register "disable_c1_state_auto_demotion" = "true"
|
||||
# Disable PKGC-state auto-demotion
|
||||
register "disable_package_c_state_demotion" = "true"
|
||||
|
||||
# Enable Energy Reporting
|
||||
register "pch_pm_energy_report_enable" = "true"
|
||||
|
||||
# Enable CNVi BT
|
||||
register "cnvi_bt_core" = "true"
|
||||
|
||||
register "serial_io_uart_mode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "pch_hda_dsp_enable" = "true"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_codec_enable" = "true"
|
||||
register "pch_hda_sdi_enable" = "{ true, false }"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on end
|
||||
device ref npu on end
|
||||
device ref xhci on end
|
||||
device ref pmc_shared_sram on end
|
||||
device ref heci1 on end
|
||||
device ref uart0 on end
|
||||
device ref soc_espi on
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_EC_H__
|
||||
#define __BASEBOARD_EC_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <ec/ec.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
/*
|
||||
* EC can wake from S3/S0ix with:
|
||||
* 1. Lid open
|
||||
* 2. AC Connect/Disconnect
|
||||
* 3. Power button
|
||||
* 4. Key press
|
||||
* 5. Mode change
|
||||
* 6. Low battery
|
||||
*/
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
|
||||
MAINBOARD_EC_S5_WAKE_EVENTS)
|
||||
#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) | \
|
||||
MAINBOARD_EC_S3_WAKE_EVENTS)
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN))
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable Keyboard Backlight */
|
||||
#define EC_ENABLE_KEYBOARD_BACKLIGHT
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
|
||||
/* Enable MKBP for buttons and switches */
|
||||
#define EC_ENABLE_MKBP_DEVICE
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
#if !CONFIG(BOARD_GOOGLE_OCELOT)
|
||||
#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */
|
||||
#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */
|
||||
#endif
|
||||
|
||||
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
|
||||
#endif /* __BASEBOARD_EC_H__ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
/*
|
||||
* EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support
|
||||
* GPIO_PCH_WP - WP signal to PCH
|
||||
*/
|
||||
//TODO for Nuvo: #define EC_SYNC_IRQ GPP_E07_IRQ
|
||||
#if CONFIG(BOARD_GOOGLE_OCELOT)
|
||||
#define EC_SYNC_IRQ 0 /* Not Connected */
|
||||
#endif
|
||||
#define GPIO_PCH_WP GPP_D02
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* SPDX-License-Identifier: GPL-3.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
static const struct mb_cfg baseboard_memcfg = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
/* TODO: Add Memory configuration */
|
||||
.ect = 1, /* Early Command Training */
|
||||
};
|
||||
|
||||
const struct mb_cfg *__weak variant_memory_params(void)
|
||||
{
|
||||
return &baseboard_memcfg;
|
||||
}
|
||||
|
||||
int __weak variant_memory_sku(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool __weak variant_is_half_populated(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __weak variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
|
||||
spd_info->cbfs_index = variant_memory_sku();
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
|
||||
/*
|
||||
* SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
|
||||
* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
|
||||
*/
|
||||
const struct cpu_tdp_power_limits power_optimized_limits[] = {
|
||||
{
|
||||
.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
|
||||
.cpu_tdp = TDP_25W,
|
||||
.power_limits_index = PTL_H_1_CORE,
|
||||
.pl1_min_power = 10000,
|
||||
.pl1_max_power = 25000,
|
||||
.pl2_min_power = 50000,
|
||||
.pl2_max_power = 50000,
|
||||
.pl4_power = 65000
|
||||
},
|
||||
{
|
||||
.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
|
||||
.cpu_tdp = TDP_25W,
|
||||
.power_limits_index = PTL_H_1_CORE,
|
||||
.pl1_min_power = 10000,
|
||||
.pl1_max_power = 25000,
|
||||
.pl2_min_power = 50000,
|
||||
.pl2_max_power = 50000,
|
||||
.pl4_power = 65000
|
||||
},
|
||||
{
|
||||
.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
|
||||
.cpu_tdp = TDP_25W,
|
||||
.power_limits_index = PTL_H_2_CORE,
|
||||
.pl1_min_power = 10000,
|
||||
.pl1_max_power = 25000,
|
||||
.pl2_min_power = 50000,
|
||||
.pl2_max_power = 50000,
|
||||
.pl4_power = 65000
|
||||
},
|
||||
{
|
||||
.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
|
||||
.cpu_tdp = TDP_25W,
|
||||
.power_limits_index = PTL_H_2_CORE,
|
||||
.pl1_min_power = 10000,
|
||||
.pl1_max_power = 25000,
|
||||
.pl2_min_power = 50000,
|
||||
.pl2_max_power = 50000,
|
||||
.pl4_power = 65000
|
||||
},
|
||||
};
|
||||
|
||||
void baseboard_devtree_update(void)
|
||||
{
|
||||
/* Don't optimize the power limit if booting with barrel attached */
|
||||
if (google_chromeec_is_barrel_charger_present())
|
||||
return;
|
||||
|
||||
if (!google_chromeec_is_battery_present())
|
||||
variant_update_cpu_power_limits(power_optimized_limits,
|
||||
ARRAY_SIZE(power_optimized_limits));
|
||||
}
|
||||
9
src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
Normal file
9
src/mainboard/google/ocelot/variants/ocelot/Makefile.mk
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
romstage-y += memory.c
|
||||
romstage-$(CONFIG_FW_CONFIG) += fw_config.c
|
||||
ramstage-y += gpio.c
|
||||
ramstage-$(CONFIG_FW_CONFIG) += variant.c
|
||||
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
|
||||
651
src/mainboard/google/ocelot/variants/ocelot/fw_config.c
Normal file
651
src/mainboard/google/ocelot/variants/ocelot/fw_config.c
Normal file
|
|
@ -0,0 +1,651 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <console/console.h>
|
||||
#include <fw_config.h>
|
||||
#include <gpio.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
/* t: base table; o: override table */
|
||||
#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
|
||||
/* t: table */
|
||||
#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
|
||||
|
||||
static const struct pad_config i2s_enable_pads[] = {
|
||||
/* I2S_MCLK1_OUT */
|
||||
PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
|
||||
/* I2S0_SCLK_HDR */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
|
||||
/* I2S0_SFRM_HDR */
|
||||
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
|
||||
/* I2S0_TXD_HDR */
|
||||
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
|
||||
/* I2S0_RXD_HDR */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
|
||||
/* I2S1_SCLK_HDR */
|
||||
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6),
|
||||
/* I2S1_SFRM_HDR */
|
||||
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6),
|
||||
/* I2S1_TXD_HDR */
|
||||
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6),
|
||||
/* I2S1_RXD_HDR */
|
||||
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6),
|
||||
|
||||
/* DMIC_CLK */
|
||||
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
|
||||
/* DMIC_DATA */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
|
||||
|
||||
/* DMIC_CLK */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
|
||||
/* DMIC_DATA */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
|
||||
};
|
||||
|
||||
static const struct pad_config hda_enable_pads[] = {
|
||||
/* HDA_BCLK */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
/* HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
|
||||
/* HDA_SDO */
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
|
||||
/* HDA_SDI_0 */
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
|
||||
/* HDA_RST_B */
|
||||
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
|
||||
/* HDA_SDI_1 */
|
||||
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1),
|
||||
|
||||
/* DMIC_CLK */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
|
||||
/* DMIC_DATA */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
|
||||
};
|
||||
|
||||
static const struct pad_config sndw_external_codec_enable_pads[] = {
|
||||
/* Soundwire - External codec - JE Header */
|
||||
/* SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
|
||||
/* SNDW3_DATA0 */
|
||||
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
|
||||
/* SNDW0_CLK */
|
||||
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
|
||||
/* SNDW0_DATA */
|
||||
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
|
||||
/* SNDW2_CLK */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
|
||||
/* SNDW2_DATA */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
|
||||
/* SNDW1_CLK */
|
||||
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
|
||||
/* SNDW1_DATA */
|
||||
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
|
||||
|
||||
/* GPP_D13: RST_HP_L */
|
||||
PAD_CFG_GPO(GPP_D13, 1, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config bt_i2s_enable_pads[] = {
|
||||
/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
|
||||
PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
|
||||
/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
|
||||
PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
|
||||
/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
|
||||
PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
|
||||
/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
|
||||
PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
|
||||
/* GPP_V34 : [] ==> SSP_SCLK */
|
||||
PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
|
||||
/* GPP_V35 : [] ==> SSP_SFRM */
|
||||
PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
|
||||
/* GPP_V36 : [] ==> SSP_TXD */
|
||||
PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
|
||||
/* GPP_V37 : [] ==> SSP_RXD */
|
||||
PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
static const struct pad_config bt_i2s_disable_pads[] = {
|
||||
/* GPP_V30 : [] ==> BT_I2S_BCLK */
|
||||
PAD_NC(GPP_VGPIO30, NONE),
|
||||
/* GPP_V31 : [] ==> BT_I2S_SYNC */
|
||||
PAD_NC(GPP_VGPIO31, NONE),
|
||||
/* GPP_V32 : [] ==> BT_I2S_SDO */
|
||||
PAD_NC(GPP_VGPIO32, NONE),
|
||||
/* GPP_V33 : [] ==> BT_I2S_SDI */
|
||||
PAD_NC(GPP_VGPIO33, NONE),
|
||||
/* GPP_V34 : [] ==> SSP2_SCLK */
|
||||
PAD_NC(GPP_VGPIO34, NONE),
|
||||
/* GPP_V35 : [] ==> SSP2_SFRM */
|
||||
PAD_NC(GPP_VGPIO35, NONE),
|
||||
/* GPP_V36 : [] ==> SSP_TXD */
|
||||
PAD_NC(GPP_VGPIO36, NONE),
|
||||
/* GPP_V37 : [] ==> SSP_RXD */
|
||||
PAD_NC(GPP_VGPIO37, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config sndw_alc722_enable_pads[] = {
|
||||
/* SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
|
||||
/* SNDW3_DATA0 */
|
||||
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
|
||||
/* SNDW3_DATA1 */
|
||||
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
|
||||
/* SNDW3_DATA2 */
|
||||
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
|
||||
/* DMIC_CLK_A0 */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
|
||||
/* DMIC_DATA_0 */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
|
||||
/* SNDW1_CLK */
|
||||
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
|
||||
/* SNDW1_DATA */
|
||||
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
|
||||
|
||||
/* DMIC_CLK */
|
||||
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
|
||||
/* DMIC_DATA */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
|
||||
};
|
||||
|
||||
static const struct pad_config audio_disable_pads[] = {
|
||||
PAD_NC(GPP_S00, NONE),
|
||||
PAD_NC(GPP_S01, NONE),
|
||||
PAD_NC(GPP_S02, NONE),
|
||||
PAD_NC(GPP_S03, NONE),
|
||||
PAD_NC(GPP_S04, NONE),
|
||||
PAD_NC(GPP_S05, NONE),
|
||||
PAD_NC(GPP_S06, NONE),
|
||||
PAD_NC(GPP_S07, NONE),
|
||||
PAD_NC(GPP_D09, NONE),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config pre_mem_x1slot_pads[] = {
|
||||
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_A08, 0, PLTRST),
|
||||
};
|
||||
static const struct pad_config x1slot_pads[] = {
|
||||
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
|
||||
/* GPP_D19: X1_DT_PCIE_RST_N */
|
||||
PAD_CFG_GPO(GPP_D19, 1, PLTRST),
|
||||
/* GPP_B25: X1_SLOT_WAKE_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
|
||||
};
|
||||
|
||||
static const struct pad_config x1slot_disable_pads[] = {
|
||||
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_A08, 0, PLTRST),
|
||||
/* GPP_D19: X1_DT_PCIE_RST_N */
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
/* GPP_B25: X1_SLOT_WAKE_N */
|
||||
PAD_NC(GPP_B25, NONE)
|
||||
};
|
||||
|
||||
/*
|
||||
* WWAN: power sequence requires three stages:
|
||||
* step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off
|
||||
* step 2: deassert FCP#
|
||||
* step 3: deassert RST# first, and then PERST#.
|
||||
* NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen
|
||||
* at much later time and time between RST# and PERSET# is guaranteed.
|
||||
*/
|
||||
static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = {
|
||||
/* GPP_H16: WWAN_PWREN */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
|
||||
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
|
||||
PAD_CFG_GPO(GPP_A09, 0, PLTRST),
|
||||
/* GPP_B20: M.2_WWAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_B20, 0, PLTRST),
|
||||
/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
|
||||
PAD_CFG_GPO(GPP_D03, 0, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = {
|
||||
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
|
||||
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config wwan_pwr_seq3_pads[] = {
|
||||
/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
|
||||
PAD_CFG_GPO(GPP_D03, 1, PLTRST),
|
||||
/* GPP_B20: M.2_WWAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
|
||||
/* GPP_E02: WWAN_WAKE_GPIO_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
|
||||
};
|
||||
|
||||
static const struct pad_config wwan_disable_pads[] = {
|
||||
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
|
||||
PAD_NC(GPP_A09, NONE),
|
||||
/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
|
||||
PAD_NC(GPP_D03, NONE),
|
||||
/* GPP_B20: M.2_WWAN_RST_N */
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
/* GPP_H16: WWAN_PWREN */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* GPP_A10: M.2_WWAN_DISABLE_N */
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
/* GPP_E02: WWAN_WAKE_GPIO_N */
|
||||
PAD_NC(GPP_E02, NONE),
|
||||
};
|
||||
|
||||
/* Gen4 NVME: at the top M.2 slot */
|
||||
static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
|
||||
/* GPP_B10: GEN4_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B10, 0, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config gen4_ssd_pads[] = {
|
||||
/* GPP_B10: GEN4_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B10, 1, PLTRST),
|
||||
/* GPP_B09: M2_GEN4_SSD_RESET_N */
|
||||
PAD_CFG_GPO(GPP_B09, 1, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config ufs_enable_pads[] = {
|
||||
/* GPP_D21: GPP_D21_UFS_REFCLK */
|
||||
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Gen5 NVME: at the bottom M.2 slot */
|
||||
static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
|
||||
/* GPP_B16: GEN5_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B16, 0, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config gen5_ssd_pads[] = {
|
||||
/* GPP_B16: GEN5_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
|
||||
/* GPP_E03: M2_GEN5_SSD_RESET_N */
|
||||
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
|
||||
};
|
||||
|
||||
static const struct pad_config peg_x4slot_wake_disable_pads[] = {
|
||||
/* GPP_D24: PEG_SLOT_WAKE_N */
|
||||
PAD_NC(GPP_D24, NONE),
|
||||
/* GPP_D25: X4_SLOT_WAKE_N */
|
||||
PAD_NC(GPP_D25, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config pcie_wlan_enable_pads[] = {
|
||||
/* GPP_A11: WLAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_A11, 1, PLTRST),
|
||||
/* GPP_A12: WIFI_WAKE_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
|
||||
};
|
||||
|
||||
static const struct pad_config pcie_wlan_disable_pads[] = {
|
||||
/* GPP_A11: WLAN_RST_N */
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
/* GPP_A12: WIFI_WAKE_N */
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config cnvi_enable_pads[] = {
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
|
||||
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
|
||||
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
|
||||
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
|
||||
/* GPP_F04: CNV_RF_RESET_R_N */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
|
||||
/* GPP_F05: CRF_CLKREQ_R */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
|
||||
/* GPP_A16: BT_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A16, 1, DEEP),
|
||||
/* GPP_A17: WIFI_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A17, 1, DEEP),
|
||||
};
|
||||
|
||||
static const struct pad_config cnvi_disable_pads[] = {
|
||||
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
|
||||
PAD_NC(GPP_F00, NONE),
|
||||
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
|
||||
PAD_NC(GPP_F01, NONE),
|
||||
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
|
||||
PAD_NC(GPP_F02, NONE),
|
||||
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
PAD_NC(GPP_F03, NONE),
|
||||
/* GPP_F04: CNV_RF_RESET_R_N */
|
||||
PAD_NC(GPP_F04, NONE),
|
||||
/* GPP_F05: CRF_CLKREQ_R */
|
||||
PAD_NC(GPP_F05, NONE),
|
||||
|
||||
/* GPP_A16: BT_RF_KILL_N */
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
/* GPP_A17: WIFI_RF_KILL_N */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config touchscreen_disable_pads[] = {
|
||||
/* GPP_F08: TCH_PNL1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_F08, 0, PLTRST),
|
||||
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
|
||||
PAD_NC(GPP_E14, NONE),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = {
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
|
||||
PAD_NC(GPP_E14, NONE),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config touchscreen_thc_i2c_enable_pads[] = {
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
|
||||
PAD_NC(GPP_E14, NONE),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config touchscreen_gspi_enable_pads[] = {
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
|
||||
PAD_NC(GPP_E14, NONE),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT)
|
||||
};
|
||||
|
||||
static const struct pad_config touchscreen_thc_spi_enable_pads[] = {
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 NF3: THC HID-SPI */
|
||||
/* THC NOTE: use GPO instead of NF for THC0 Rst */
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
|
||||
};
|
||||
|
||||
static const struct pad_config touchpad_thc_i2c_enable_pads[] = {
|
||||
/* GPP_F12: NF1: thc_i2c1_scl */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* GPP_F13: NF1: thc_i2c1_sda */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
|
||||
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
|
||||
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
|
||||
/* GPP_A13: TCH_PAD_INT_N */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT),
|
||||
};
|
||||
|
||||
static const struct pad_config touchpad_i2c_disable_pads[] = {
|
||||
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
/* GPP_A13: TCH_PAD_INT_N */
|
||||
PAD_NC(GPP_A13, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config ish_disable_pads[] = {
|
||||
/* GPP_D06: NC */
|
||||
PAD_NC(GPP_D06, NONE),
|
||||
/* GPP_E05: NC */
|
||||
PAD_NC(GPP_E05, NONE),
|
||||
/* GPP_F23: NC */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config ish_enable_pads[] = {
|
||||
/* GPP_D06: ISH_UART0_TXD */
|
||||
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
|
||||
/* GPP_E05: ISH_GP_7_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
|
||||
/* GPP_F23: ISH_GP_9A */
|
||||
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
|
||||
};
|
||||
|
||||
static const struct pad_config fp_disable_pads[] = {
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
|
||||
PAD_CFG_GPO(GPP_D01, 1, DEEP),
|
||||
/* FIXME: b/390031369
|
||||
* use dedicated GPIO PIN for codec enable
|
||||
* when FPS is enabled.
|
||||
*/
|
||||
/* GPP_E19: CODEC_EN */
|
||||
PAD_CFG_GPO(GPP_E19, 1, PLTRST),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
};
|
||||
|
||||
static const struct pad_config fp_enable_pads[] = {
|
||||
/* GPP_C15: FPS_RST_N */
|
||||
PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
|
||||
/* GPP_D01: FPS_SOC_INT_L */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
|
||||
/* GPP_E19: FPMCU_PWREN */
|
||||
PAD_CFG_GPO(GPP_E19, 1, DEEP),
|
||||
/* GPP_E20: FPMCU_FW_UPDATE */
|
||||
PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
|
||||
/* GPP_F14: GPSI0A_MOSI */
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
|
||||
/* GPP_F15: GSPI0A_MISO */
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
|
||||
/* GPP_F16: GPSI0A_CLK */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
|
||||
/* GPP_F18: GSPI0A_CS0 */
|
||||
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
|
||||
};
|
||||
|
||||
static const struct pad_config pre_mem_fp_enable_pads[] = {
|
||||
/* GPP_C15: FPS_RST_N */
|
||||
PAD_CFG_GPO(GPP_C15, 0, DEEP),
|
||||
};
|
||||
|
||||
void fw_config_configure_pre_mem_gpio(void)
|
||||
{
|
||||
if (!fw_config_is_provisioned()) {
|
||||
printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
|
||||
GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
|
||||
GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
|
||||
GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
|
||||
GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
|
||||
GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
|
||||
}
|
||||
|
||||
if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
|
||||
GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
|
||||
|
||||
/*
|
||||
* NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
|
||||
* FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V
|
||||
* and FCP#) is '0'. Therefore, it will be fine even though there is no
|
||||
* GPIO configured for other PADs via fw_config to have the time delay
|
||||
* introduced in between sequence 1 and 2. Also, FCP# was not the last PAD
|
||||
* configured in sequence 1. Although the Tpr is '0' in the datasheet, three
|
||||
* stages are preserved at this time to guarantee the sequence shown in the
|
||||
* datasheet timing diagram.
|
||||
*/
|
||||
if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT)))
|
||||
GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
|
||||
GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads);
|
||||
|
||||
}
|
||||
|
||||
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
|
||||
{
|
||||
if (!fw_config_is_provisioned()) {
|
||||
printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) {
|
||||
printk(BIOS_INFO, "Configure GPIOs for I2S MAX98360 ALC5682 audio.\n");
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads);
|
||||
printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
|
||||
fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
|
||||
printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads);
|
||||
printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
|
||||
printk(BIOS_INFO, "Configure GPIOs for HDA ALC 256 mode.\n");
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||
|
||||
fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_7))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_enable_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads);
|
||||
} else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
|
||||
fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads);
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_disable_pads);
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) ||
|
||||
fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads);
|
||||
} else {
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads);
|
||||
}
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(SD, SD_NONE)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads);
|
||||
else
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads);
|
||||
else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads);
|
||||
else
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads);
|
||||
else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads);
|
||||
else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads);
|
||||
else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads);
|
||||
else
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
|
||||
else
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
|
||||
|
||||
/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
|
||||
GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT)))
|
||||
GPIO_CONFIGURE_PADS(fp_enable_pads);
|
||||
else
|
||||
GPIO_CONFIGURE_PADS(fp_disable_pads);
|
||||
}
|
||||
424
src/mainboard/google/ocelot/variants/ocelot/gpio.c
Normal file
424
src/mainboard/google/ocelot/variants/ocelot/gpio.c
Normal file
|
|
@ -0,0 +1,424 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* GPP_A00: ESPI_IO0_EC_R */
|
||||
/* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
|
||||
|
||||
/* GPP_A01: ESPI_IO1_EC_R */
|
||||
/* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
|
||||
|
||||
/* GPP_A02: ESPI_IO2_EC_R */
|
||||
/* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
|
||||
|
||||
/* GPP_A03: ESPI_IO3_EC_R */
|
||||
/* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
|
||||
|
||||
/* GPP_A04: ESPI_CS0_EC_R_N */
|
||||
/* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
|
||||
|
||||
/* GPP_A05: ESPI_CLK_EC_R */
|
||||
/* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
|
||||
|
||||
/* GPP_A06: ESPI_RST_EC_R_N */
|
||||
/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
|
||||
|
||||
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
|
||||
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
|
||||
/* GPP_A10: M.2_WWAN_DISABLE_N */
|
||||
PAD_CFG_GPO(GPP_A10, 1, PLTRST),
|
||||
/* GPP_A11: WLAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_A11, 1, PLTRST),
|
||||
/* GPP_A12: WIFI_WAKE_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
|
||||
/* GPP_A15: GPP_A15_DNX_FORCE_RELOAD */
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* GPP_A16: BT_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A16, 1, DEEP),
|
||||
/* GPP_A17: WIFI_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A17, 1, DEEP),
|
||||
|
||||
/* GPP_B00: USBC_SML_CLK_PD */
|
||||
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
|
||||
/* GPP_B01: USBC_SML_DATA_PD */
|
||||
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
|
||||
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
|
||||
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
|
||||
/* GPP_B04: ISH_GP_0_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
|
||||
/* GPP_B05: ISH_GP_1_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
|
||||
/* GPP_B06: ISH_GP_2_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
|
||||
/* GPP_B07: ISH_GP_3_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
|
||||
/* GPP_B08: ISH_GP_4_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
|
||||
/* GPP_B09: M2_GEN4_SSD_RESET_N */
|
||||
PAD_CFG_GPO(GPP_B09, 1, PLTRST),
|
||||
/* GPP_B10: GEN4_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B10, 1, PLTRST),
|
||||
/* GPP_B11: MOD_TCSS1_DISP_HPD3 */
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
|
||||
/* GPP_B12: PM_SLP_S0_N */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* GPP_B13: PLT_RST_N */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* GPP_B14: MOD_TCSS2_DISP_HPD4 */
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
|
||||
/* GPP_B15: MOD_TCSS_USB_TYP_A_OC3_N */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* GPP_B16: GEN5_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
|
||||
/* GPP_B17: Not used */
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
|
||||
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
|
||||
/* GPP_B20: M.2_WWAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
|
||||
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP),
|
||||
/* GPP_B22: ISH_GP_5_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
|
||||
/* GPP_B23: ISH_GP_6_SNSR_HDR */
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
|
||||
/* GPP_B24: ESPI_ALERT0_EC_R_N */
|
||||
PAD_NC(GPP_B24, NONE),
|
||||
|
||||
/* GPP_C00: GPP_C0_SMBCLK */
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
|
||||
/* GPP_C01: GPP_C1_SMBDATA */
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
|
||||
/* GPP_C02: Not used */
|
||||
PAD_NC(GPP_C02, NONE),
|
||||
/* GPP_C03: TCP_LAN_SML0_SCL_R */
|
||||
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
|
||||
/* GPP_C04: TCP_LAN_SML0_SDA_R */
|
||||
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
|
||||
/* GPP_C06: SML1_CLK */
|
||||
PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
|
||||
/* GPP_C07: SML1_DATA */
|
||||
PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
|
||||
/* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
|
||||
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
|
||||
/* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */
|
||||
PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
|
||||
/* GPP_C11: CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
|
||||
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
|
||||
/* GPP_C12: CLKREQ3_X1_GEN1_GBE_LAN_N */
|
||||
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
|
||||
/* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */
|
||||
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
|
||||
/* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */
|
||||
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
|
||||
/* GPP_C16: TBT_LSX0_TXD */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
/* GPP_C17: TBT_LSX0_RXD */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
/* GPP_C18: TBT_LSX1_TXD */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
/* GPP_C19: TBT_LSX1_RXD */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
/* GPP_C20: MOD_TCSS1_LS_TX_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
|
||||
/* GPP_C21: MOD_TCSS1_LS_RX_DDC_SDA */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
|
||||
/* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
|
||||
/* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */
|
||||
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
|
||||
|
||||
/* GPP_D00: IMGCLKOUT_1 */
|
||||
PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
|
||||
/* GPP_D02: Not used */
|
||||
PAD_NC(GPP_D02, NONE),
|
||||
/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
|
||||
PAD_CFG_GPO(GPP_D03, 1, PLTRST),
|
||||
/* GPP_D04: IMGCLKOUT_0 */
|
||||
PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
|
||||
/* GPP_D05: disable ISH_UART0_RXD */
|
||||
PAD_NC(GPP_D05, NONE),
|
||||
/* GPP_D07: NC */
|
||||
PAD_NC(GPP_D07, NONE),
|
||||
/* GPP_D08: NC */
|
||||
PAD_NC(GPP_D08, NONE),
|
||||
/* GPP_D09: PEG_SLOT_RST_N */
|
||||
PAD_CFG_GPO(GPP_D09, 1, PLTRST),
|
||||
/* GPP_D10: HDA_BCLK */
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
/* GPP_D11: HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
|
||||
/* GPP_D12: HDA_SDO */
|
||||
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
|
||||
/* GPP_D13: HDA_SDI0 */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
|
||||
/* GPP_D14: COINLESS_MODE_SELECT */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
|
||||
/* GPP_D15: SPI_TPM_INT_N */
|
||||
PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
|
||||
/* GPP_D16: HDA_RST_N_HDR */
|
||||
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
|
||||
/* GPP_D17: HDA_SDI1_HDR */
|
||||
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */
|
||||
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* GPP_D20: CSE_EARLY_SW */
|
||||
PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
|
||||
/* GPP_D21: NC */
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
/* GPP_D22: BPKI3C_SDA */
|
||||
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
|
||||
/* GPP_D23: BPKI3C_SCL */
|
||||
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||
/* GPP_D24: PEG_SLOT_WAKE_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
|
||||
/* GPP_D25: X4_SLOT_WAKE_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
|
||||
|
||||
/* GPP_E01: CRD2_RST_N */
|
||||
PAD_CFG_GPO(GPP_E01, 1, PLTRST),
|
||||
/* GPP_E02: WWAN_WAKE_GPIO_N */
|
||||
PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
|
||||
/* GPP_E03: M2_GEN5_SSD_RESET_N */
|
||||
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
|
||||
/* GPP_E06: SECURE_CAM_SW */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
|
||||
#if CONFIG(BOARD_GOOGLE_OCELOT)
|
||||
/* GPP_E07: Not used */
|
||||
PAD_NC(GPP_E07, NONE),
|
||||
#else
|
||||
/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
|
||||
#endif
|
||||
/* GPP_E08: Not used */
|
||||
PAD_NC(GPP_E08, NONE),
|
||||
/* GPP_E09: USB_RD_FP_CONN_12_OC0_N */
|
||||
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
|
||||
/* GPP_E10: CRD1_RST_N */
|
||||
PAD_CFG_GPO(GPP_E10, 1, PLTRST),
|
||||
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
|
||||
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
|
||||
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
|
||||
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
|
||||
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
|
||||
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
|
||||
/* THC NOTE: use GPO instead of GPO for THC0 Rst */
|
||||
PAD_CFG_GPO(GPP_E16, 1, DEEP),
|
||||
/* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
|
||||
/* GPP_E21: I2C_PMC_PD_INT_N */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
/* GPP_E22: THC0_SPI1_DSYNC */
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
|
||||
|
||||
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
|
||||
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
|
||||
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
|
||||
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
|
||||
/* GPP_F04: CNV_RF_RESET_R_N */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
|
||||
/* GPP_F05: CRF_CLKREQ_R */
|
||||
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
|
||||
/* GPP_F06: WLAN_WWAN_COEX3 */
|
||||
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
|
||||
/* GPP_F07: IMGCLKOUT_2 */
|
||||
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
|
||||
/* GPP_F08: TCH_PNL1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
|
||||
/* GPP_F09: NC */
|
||||
PAD_NC(GPP_F09, NONE),
|
||||
/* GPP_F10: PEG_SLOT_PWR_EN_N */
|
||||
PAD_CFG_GPO(GPP_F10, 0, PLTRST),
|
||||
/* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */
|
||||
PAD_CFG_GPO(GPP_F11, 1, DEEP),
|
||||
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
|
||||
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
|
||||
/* GPP_F17: Not used */
|
||||
PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
|
||||
/* GPP_F19: GPP_PRIVACY_LED_CAM2 */
|
||||
PAD_CFG_GPO(GPP_F19, 0, PLTRST),
|
||||
/* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
|
||||
PAD_CFG_GPO(GPP_F20, 0, PLTRST),
|
||||
/* GPP_F22: THC1_SPI2_DSYNC */
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
|
||||
|
||||
/* GPP_H00: Not used */
|
||||
PAD_NC(GPP_H00, NONE),
|
||||
/* GPP_H01: CRD_CAM_STROBE */
|
||||
PAD_CFG_GPO(GPP_H01, 0, PLTRST),
|
||||
/* GPP_H02: DEBUG_TRACE_PNP */
|
||||
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
|
||||
/* GPP_H03: MIC MUTE */
|
||||
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
|
||||
/* GPP_H04: I2C2_SDA_CAM_FLSH */
|
||||
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
|
||||
/* GPP_H05: I2C2_SCL_CAM_FLSH */
|
||||
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
|
||||
/* GPP_H06: I2C3_SDA_PSS */
|
||||
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
|
||||
/* GPP_H07: I2C3_SCL_PSS */
|
||||
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
|
||||
/* GPP_H08: UART0_BUF_RXD */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: UART0_BUF_TXD */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
/* GPP_H10: UART0_BUF_RTS */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
|
||||
/* GPP_H11: UART0_BUF_CTS */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
|
||||
/* GPP_H13: CPU_C10_GATE_N_R */
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
|
||||
/* GPP_H14: NC */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* GPP_H15: NC */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* GPP_H16: WWAN_PWREN */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
|
||||
/* GPP_H17: MIC MUTE LED */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
/* GPP_H19: I3C0_SDA_HDR */
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
|
||||
/* GPP_H20: I3C0_SCL_HDR */
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
|
||||
/* GPP_H21: I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22: I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_S00: SNDW3_CLK_CODEC */
|
||||
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
|
||||
/* GPP_S01: SNDW3_DATA0_CODEC */
|
||||
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
|
||||
/* GPP_S02: SNDW3_DATA1_CODEC */
|
||||
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
|
||||
/* GPP_S03: SNDW3_DATA2_CODEC */
|
||||
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
|
||||
/* GPP_S04: SNDW2_CLK */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
|
||||
/* GPP_S05: SNDW2_DATA0 */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
|
||||
/* GPP_S06: SNDW1_CLK */
|
||||
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
|
||||
/* GPP_S07: SNDW1_DATA0 */
|
||||
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
|
||||
|
||||
/* GPP_V00: PM_BATLOW_N */
|
||||
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
|
||||
/* GPP_V01: BC_ACOK_MCP */
|
||||
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
|
||||
/* GPP_V02: LANWAKE_N_R */
|
||||
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
|
||||
/* GPP_V03: PWRBTN_MCP_N */
|
||||
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
|
||||
/* GPP_V04: PM_SLP_S3_N */
|
||||
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
|
||||
/* GPP_V05: PM_SLP_S4_N */
|
||||
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
|
||||
/* GPP_V06: PM_SLP_A_N */
|
||||
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
|
||||
/* GPP_V07: Not used */
|
||||
PAD_NC(GPP_V07, NONE),
|
||||
/* GPP_V08: SLP_WLAN_N */
|
||||
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
|
||||
/* GPP_V09: PM_SLP_S5_N */
|
||||
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
|
||||
/* GPP_V10: LANPHYPC_R_N */
|
||||
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
|
||||
/* GPP_V11: PM_SLP_LAN_N */
|
||||
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
|
||||
/* GPP_V12: WAKE_N */
|
||||
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
|
||||
/* GPP_V13: GPP_V13_CATERR_N */
|
||||
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
|
||||
/* GPP_V14: GPP_V14_FORCEPR_N */
|
||||
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
|
||||
/* GPP_V15: GPP_V15_THERMTRIP_N */
|
||||
PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
|
||||
/* GPP_V16: GPP_V16_VCCST_EN */
|
||||
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
|
||||
/* GPP_V17: TCP_RT_S0IX_ENTRY_EXIT_N */
|
||||
PAD_CFG_GPO(GPP_V17, 1, DEEP),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* GPP_H08: UART0_BUF_RXD */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: UART0_BUF_TXD */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
|
||||
/* GPP_H06: I2C3_SDA_PSS */
|
||||
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
|
||||
/* GPP_H07: I2C3_SCL_PSS */
|
||||
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
|
||||
/* GPP_D15: SPI_TPM_INT_N */
|
||||
PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
|
||||
};
|
||||
|
||||
/* Pad configuration in romstage */
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* GPP_C00: GPP_C0_SMBCLK */
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
|
||||
/* GPP_C01: GPP_C1_SMBDATA */
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Create the stub for romstage gpio, typically use for power sequence */
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
|
||||
};
|
||||
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
126
src/mainboard/google/ocelot/variants/ocelot/hda_verb.c
Normal file
126
src/mainboard/google/ocelot/variants/ocelot/hda_verb.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
|
||||
0x10ec12ac, /* Subsystem ID */
|
||||
0x00000013, /* Number of jacks (NID entries) */
|
||||
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec12ac),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
/*
|
||||
* DMIC
|
||||
* Requirement is to use PCH DMIC. Hence,
|
||||
* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
/* Pin widget 0x14 - Front (Port-D) */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
/* Pin widget 0x18 - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
/* Pin widget 0x1B - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
|
||||
/* Pin widget 0x1E - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
/* Pin widget 0x21 - HP1-OUT (Port-I) */
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/*
|
||||
* Widget node 0x20 - 1
|
||||
* Codec hidden reset and speaker power 2W/4ohm
|
||||
*/
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x02050038,
|
||||
0x02047901,
|
||||
/*
|
||||
* Widget node 0x20 - 2
|
||||
* Class D power on Reset
|
||||
*/
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/*
|
||||
* Widget node 0x20 - 3
|
||||
* Disable AGC and set AGC limit to -1.5dB
|
||||
*/
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC1,
|
||||
/*
|
||||
* Widget node 0x20 - 4
|
||||
* Set AGC Post gain +1.5dB then Enable AGC
|
||||
*/
|
||||
0x02050013,
|
||||
0x02044023,
|
||||
0x02050016,
|
||||
0x02040E50,
|
||||
/*
|
||||
* Widget node 0x20 - 5
|
||||
* Silence detector enabling + Set EAPD to verb control
|
||||
*/
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/*
|
||||
* Widget node 0x20 - 6
|
||||
* Silence data mode Threshold (-90dB)
|
||||
*/
|
||||
0x02050030,
|
||||
0x0204A000,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
/*
|
||||
* Widget node 0x20 - 7
|
||||
* Default setting-1
|
||||
*/
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/*
|
||||
* Widget node 0x20 - 8
|
||||
* support 1 pin detect two port
|
||||
*/
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/*
|
||||
* Widget node 0x20 - 9
|
||||
* To set LDO1/LDO2 as default
|
||||
*/
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x01470C00,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
0x01470740,
|
||||
/* Dos beep path - 2 */
|
||||
0x0143b000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
76
src/mainboard/google/ocelot/variants/ocelot/memory.c
Normal file
76
src/mainboard/google/ocelot/variants/ocelot/memory.c
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/meminit.h>
|
||||
|
||||
static const struct mb_cfg lp5_mem_config = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, },
|
||||
.dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, },
|
||||
.dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 },
|
||||
.dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, },
|
||||
.dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 },
|
||||
.dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, },
|
||||
.dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 9, 10, 11, 8, 14, 12, 13, 15, },
|
||||
.dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, },
|
||||
.dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 },
|
||||
},
|
||||
},
|
||||
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
|
||||
},
|
||||
|
||||
.ect = true, /* Early Command Training */
|
||||
|
||||
.lp_ddr_dq_dqs_re_training = 1,
|
||||
|
||||
.user_bd = BOARD_TYPE_ULT_ULX,
|
||||
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xFF,
|
||||
},
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &lp5_mem_config;
|
||||
}
|
||||
|
||||
void variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
|
||||
spd_info->cbfs_index = 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ocelot/memory src/mainboard/google/ocelot/variants/ocelot/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
H58G56BK7BX068 0 (0000)
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# This is a CSV file containing a list of memory parts used by this variant.
|
||||
# One part per line with an optional fixed ID in column 2.
|
||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
H58G56BK7BX068
|
||||
890
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
Normal file
890
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
Normal file
|
|
@ -0,0 +1,890 @@
|
|||
fw_config
|
||||
field AUDIO 0 3
|
||||
option AUDIO_NONE 0
|
||||
option AUDIO_MAX98373_ALC5682_SNDW 1
|
||||
option AUDIO_ALC722_SNDW 2
|
||||
option AUDIO_ALC256_HDA 3
|
||||
option AUDIO_MAX98360_ALC5682I_I2S 4
|
||||
option AUDIO_ALC721_SNDW 5
|
||||
end
|
||||
field WIFI 4 5
|
||||
option WIFI_CNVI_6 0
|
||||
option WIFI_CNVI_7 1
|
||||
option WIFI_PCIE_6 2
|
||||
option WIFI_PCIE_7 3
|
||||
end
|
||||
field CELLULAR 6 7
|
||||
option CELLULAR_ABSENT 0
|
||||
option CELLULAR_USB 1
|
||||
option CELLULAR_PCIE 2
|
||||
end
|
||||
field TOUCHSCREEN 8 10
|
||||
option TOUCHSCREEN_NONE 0
|
||||
option TOUCHSCREEN_LPSS_I2C 1
|
||||
option TOUCHSCREEN_GSPI 2
|
||||
option TOUCHSCREEN_THC_SPI 3
|
||||
option TOUCHSCREEN_THC_I2C 4
|
||||
end
|
||||
field TOUCHPAD 11 12
|
||||
option TOUCHPAD_NONE 0
|
||||
option TOUCHPAD_THC_I2C 1
|
||||
option TOUCHPAD_LPSS_I2C 2
|
||||
end
|
||||
field SD 13 14
|
||||
option SD_NONE 0
|
||||
option SD_GENSYS 1
|
||||
option SD_BAYHUB 2
|
||||
end
|
||||
field STORAGE 15 16
|
||||
option STORAGE_UNKNOWN 0
|
||||
option STORAGE_NVME_GEN4 1
|
||||
option STORAGE_NVME_GEN5 2
|
||||
option STORAGE_UFS 3
|
||||
end
|
||||
field FP 17
|
||||
option FP_ABSENT 0
|
||||
option FP_PRESENT 1
|
||||
end
|
||||
field DISPLAY 18
|
||||
option DISPLAY_ABSENT 0
|
||||
option DISPLAY_PRESENT 1
|
||||
end
|
||||
field KB 19
|
||||
option KB_ABSENT 0
|
||||
option KB_PRESENT 1
|
||||
end
|
||||
field UFC 20 21
|
||||
option UFC_ABSENT 0
|
||||
option UFC_MIPI 1
|
||||
option UFC_USB 2
|
||||
end
|
||||
field WFC 22 23
|
||||
option WFC_ABSENT 0
|
||||
option WFC_MIPI 1
|
||||
option WFC_USB 2
|
||||
end
|
||||
field ISH 24
|
||||
option ISH_DISABLE 0
|
||||
option ISH_ENABLE 1
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/pantherlake
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
|
||||
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
|
||||
# Enable EDP in PortA
|
||||
register "ddi_port_A_config" = "1"
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD,
|
||||
}"
|
||||
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C1 | Camera(CRD1) |
|
||||
#| I2C2 | Camera(CRD2) |
|
||||
#| I2C3 | Audio, TPM(cr50) |
|
||||
#| I2C4 | Touchscreen |
|
||||
#| I2C5 | Touchpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on
|
||||
probe DISPLAY DISPLAY_PRESENT
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "5"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) for port C1
|
||||
register "device[3].name" = ""DD03""
|
||||
register "device[3].use_pld" = "true"
|
||||
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
# TCP2 (DP-3) for port C2
|
||||
register "device[4].name" = ""DD04""
|
||||
register "device[4].use_pld" = "true"
|
||||
register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DDR_SOC""
|
||||
register "options.tsr[1].desc" = ""Ambient""
|
||||
register "options.tsr[2].desc" = ""Charger""
|
||||
register "options.tsr[3].desc" = ""wwan""
|
||||
|
||||
## Active Policy
|
||||
# FIXME: below values are initial reference values only
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 97),
|
||||
TEMP_PCT(65, 90),
|
||||
TEMP_PCT(60, 80),
|
||||
TEMP_PCT(55, 75),
|
||||
TEMP_PCT(50, 65),
|
||||
TEMP_PCT(45, 45),
|
||||
TEMP_PCT(43, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 97),
|
||||
TEMP_PCT(65, 90),
|
||||
TEMP_PCT(60, 80),
|
||||
TEMP_PCT(55, 75),
|
||||
TEMP_PCT(50, 65),
|
||||
TEMP_PCT(45, 45),
|
||||
TEMP_PCT(43, 30),
|
||||
}
|
||||
},
|
||||
[2] = {
|
||||
.target = DPTF_TEMP_SENSOR_2,
|
||||
.thresholds = {
|
||||
TEMP_PCT(75, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
TEMP_PCT(65, 70),
|
||||
TEMP_PCT(60, 50),
|
||||
}
|
||||
},
|
||||
[3] = {
|
||||
.target = DPTF_TEMP_SENSOR_3,
|
||||
.thresholds = {
|
||||
TEMP_PCT(75, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
TEMP_PCT(65, 70),
|
||||
TEMP_PCT(60, 60),
|
||||
TEMP_PCT(55, 50),
|
||||
TEMP_PCT(50, 40),
|
||||
TEMP_PCT(45, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
|
||||
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
|
||||
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
|
||||
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
|
||||
}"
|
||||
|
||||
## Power Limits Control
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 25000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 95000,
|
||||
.max_power = 95000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
register "cio2_num_ports" = "2"
|
||||
register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0""
|
||||
register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1""
|
||||
register "cio2_prt[0]" = "0"
|
||||
register "cio2_prt[1]" = "2"
|
||||
device generic 0 on
|
||||
probe UFC UFC_MIPI
|
||||
probe WFC WFC_MIPI
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref iaa off end
|
||||
|
||||
device ref thc0 on
|
||||
probe TOUCHSCREEN TOUCHSCREEN_THC_SPI
|
||||
probe TOUCHSCREEN TOUCHSCREEN_THC_I2C
|
||||
# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
|
||||
probe TOUCHPAD TOUCHPAD_THC_I2C
|
||||
end
|
||||
device ref thc1 on
|
||||
probe TOUCHPAD TOUCHPAD_THC_I2C
|
||||
end
|
||||
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tbt_pcie_rp1 on end
|
||||
device ref tbt_pcie_rp2 on end
|
||||
device ref tbt_pcie_rp3 on end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(4, 2)"
|
||||
device ref tcss_usb3_port0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(3, 2)"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C3""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port0 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port1 as dfp[1].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma1 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port2 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port3 as dfp[1].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref ish on
|
||||
probe ISH ISH_ENABLE
|
||||
probe FP FP_PRESENT
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(3, 1)"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C3""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(4, 1)"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(5, 1)"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(6, 1)"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 3""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(7, 1)"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port 2""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref ufs on
|
||||
probe STORAGE STORAGE_UFS
|
||||
probe STORAGE STORAGE_UNKNOWN
|
||||
end
|
||||
|
||||
device ref pcie_rp2 on
|
||||
probe CELLULAR CELLULAR_PCIE
|
||||
register "pcie_rp[PCIE_RP(2)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
|
||||
register "reset_off_delay_ms" = "20"
|
||||
register "srcclk_pin" = "5"
|
||||
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
|
||||
register "skip_on_off_support" = "true"
|
||||
register "use_rp_mutex" = "true"
|
||||
device generic 0 alias rp2_rtd3 on end
|
||||
end
|
||||
chip drivers/wwan/fm
|
||||
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)"
|
||||
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)"
|
||||
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
use rp2_rtd3 as rtd3dev
|
||||
device generic 0 on end
|
||||
end
|
||||
end # WWAN
|
||||
device ref pcie_rp3 on
|
||||
probe SD SD_GENSYS
|
||||
probe SD SD_BAYHUB
|
||||
# Enable PCH PCIE x1 slot using CLK 3
|
||||
register "pcie_rp[PCIE_RP(3)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
|
||||
register "enable_delay_ms" = "100"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
|
||||
register "reset_delay_ms" = "20"
|
||||
register "srcclk_pin" = "2"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # PCIE x1 slot
|
||||
device ref pcie_rp4 on
|
||||
probe WIFI WIFI_PCIE_6
|
||||
probe WIFI WIFI_PCIE_7
|
||||
register "pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 4,
|
||||
.clk_req = 4,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
|
||||
register "srcclk_pin" = "4"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
chip drivers/wifi/generic
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "wake" = "GPE0_DW0_12" # GPP_A12
|
||||
use usb2_port7 as bluetooth_companion
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # discrete WLAN
|
||||
device ref pcie_rp5 on
|
||||
probe STORAGE STORAGE_NVME_GEN4
|
||||
probe STORAGE STORAGE_UNKNOWN
|
||||
register "pcie_rp[PCIE_RP(5)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "is_storage" = "true"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
|
||||
register "srcclk_pin" = "6"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Gen4 M.2 SSD
|
||||
device ref pcie_rp9 on
|
||||
probe STORAGE STORAGE_NVME_GEN5
|
||||
probe STORAGE STORAGE_UNKNOWN
|
||||
register "pcie_rp[PCIE_RP(9)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "is_storage" = "true"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
|
||||
register "srcclk_pin" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Gen5 M.2 SSD
|
||||
device ref cnvi_wifi on
|
||||
probe WIFI WIFI_CNVI_6
|
||||
probe WIFI WIFI_CNVI_7
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # CNVi
|
||||
# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
|
||||
# TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways.
|
||||
device ref i2c0 on end
|
||||
device ref i2c1 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTIDB10""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 13b10 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM1""
|
||||
|
||||
register "ssdb.lanes_used" = "4"
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "560 * MHz" # 560 MHz
|
||||
register "remote_name" = ""IPU0""
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0
|
||||
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on
|
||||
probe WFC WFC_MIPI
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "3"
|
||||
register "acpi_name" = ""VCM1""
|
||||
register "chip_name" = ""DW AF VCM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "vcm_compat" = ""dongwoon,dw9714""
|
||||
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 0C on
|
||||
probe WFC WFC_MIPI
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM1""
|
||||
register "chip_name" = ""BRCA016GWZ""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "nvm_compat" = ""atmel,24c16""
|
||||
|
||||
register "nvm_size" = "0x800"
|
||||
register "nvm_pagesize" = "0x01"
|
||||
register "nvm_readonly" = "0x01"
|
||||
register "nvm_width" = "0x08"
|
||||
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 50 on
|
||||
probe WFC WFC_MIPI
|
||||
end
|
||||
end
|
||||
end # I2C1
|
||||
device ref i2c2 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTIDB10""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM1""
|
||||
register "chip_name" = ""Ov 13b10 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM1""
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "560 * MHz" # 560 MHz
|
||||
register "remote_name" = ""IPU0""
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1
|
||||
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on
|
||||
probe UFC UFC_MIPI
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "3"
|
||||
register "acpi_name" = ""VCM1""
|
||||
register "chip_name" = ""DW AF VCM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "vcm_compat" = ""dongwoon,dw9714""
|
||||
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 0C on
|
||||
probe UFC UFC_MIPI
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM1""
|
||||
register "chip_name" = ""BRCA016GWZ""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "nvm_compat" = ""atmel,24c16""
|
||||
|
||||
register "nvm_size" = "0x800"
|
||||
register "nvm_pagesize" = "0x01"
|
||||
register "nvm_readonly" = "0x01"
|
||||
register "nvm_width" = "0x08"
|
||||
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0"
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 50 on
|
||||
probe UFC UFC_MIPI
|
||||
end
|
||||
end
|
||||
end # I2C2
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on
|
||||
probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # I2C3
|
||||
device ref i2c4 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN6918""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.reset_off_delay_ms" = "2"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
|
||||
register "generic.enable_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 16 on
|
||||
probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C
|
||||
end
|
||||
end
|
||||
end # I2C4
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""HFW68H""
|
||||
register "generic.desc" = ""Hynitron TOUCHPAD""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A13_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW0_13"
|
||||
register "generic.uid" = "5"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on
|
||||
probe TOUCHPAD TOUCHPAD_LPSS_I2C
|
||||
end
|
||||
end
|
||||
end # I2C5
|
||||
|
||||
device ref gspi0 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
|
||||
register "wake" = "GPE0_DW1_01"
|
||||
register "has_power_resource" = "true"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on
|
||||
probe FP FP_PRESENT
|
||||
end
|
||||
end # FPMCU
|
||||
end
|
||||
|
||||
device ref smbus on end
|
||||
device ref npk on end
|
||||
device ref hda on
|
||||
chip drivers/intel/soundwire
|
||||
device generic 0 on
|
||||
chip drivers/soundwire/alc711
|
||||
register "desc" = ""Headset Codec""
|
||||
register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
|
||||
register "alc711_address.class" = "MIPI_CLASS_SDCA"
|
||||
register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722"
|
||||
# SoundWire Link 1 ID 1
|
||||
device generic 1.1 on
|
||||
probe AUDIO AUDIO_ALC722_SNDW
|
||||
end
|
||||
end
|
||||
chip drivers/soundwire/alc711
|
||||
register "desc" = ""Headset Codec""
|
||||
register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2"
|
||||
register "alc711_address.class" = "MIPI_CLASS_SDCA"
|
||||
register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721"
|
||||
# SoundWire Link 3 ID 1
|
||||
device generic 3.1 on
|
||||
probe AUDIO AUDIO_ALC721_SNDW
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
chip drivers/generic/max98357a
|
||||
register "hid" = ""MX98360A""
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on
|
||||
probe AUDIO AUDIO_MAX98360_ALC5682I_I2S
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
30
src/mainboard/google/ocelot/variants/ocelot/variant.c
Normal file
30
src/mainboard/google/ocelot/variants/ocelot/variant.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpigen.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
|
||||
{
|
||||
config->cnvi_wifi_core = false;
|
||||
config->cnvi_bt_core = false;
|
||||
/* CNVi */
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) ||
|
||||
fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) {
|
||||
config->cnvi_wifi_core = true;
|
||||
config->cnvi_bt_core = true;
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S)) ||
|
||||
fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) ||
|
||||
fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
|
||||
printk(BIOS_INFO, "BT audio offload configured.\n");
|
||||
config->cnvi_bt_audio_offload = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue