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mb/starlabs/*: Set tcc_offset instead of pch_thermal_trip

Browse source 
Some boards configure pch_thermal_trip based on the performance
profile, and some set tcc_offset.

tcc_offset makes more sense here, so change all the boards to be
the same.

Change-Id: Id55b5d971c895baa1ba97137351fbd0aea3317d8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86728
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-03-05 11:39:47 +00:00
commit 39244ba676
7 changed files with 21 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

9
src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_4core =
&cfg->power_limits_config[ADL_N_041_6W_CORE];
@ -34,15 +31,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 30;
cfg->tcc_offset = 30;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 25;
cfg->tcc_offset = 25;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
}

9
src/mainboard/starlabs/starbook/variants/adl/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_10core =
&cfg->power_limits_config[ADL_P_282_442_482_28W_CORE];
@ -38,15 +35,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 15;
cfg->tcc_offset = 15;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 10;
cfg->tcc_offset = 10;
break;
}

9
src/mainboard/starlabs/starbook/variants/adl_n/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_4core =
&cfg->power_limits_config[ADL_N_041_6W_CORE];
@ -33,15 +30,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 15;
cfg->tcc_offset = 15;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 10;
cfg->tcc_offset = 10;
break;
}

9
src/mainboard/starlabs/starbook/variants/mtl/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_20core =
&cfg->power_limits_config[MTL_P_682_482_CORE];
@ -33,15 +30,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 30;
cfg->tcc_offset = 30;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 25;
cfg->tcc_offset = 25;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
}

9
src/mainboard/starlabs/starbook/variants/rpl/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_6core =
&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
@ -40,15 +37,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 30;
cfg->tcc_offset = 30;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 25;
cfg->tcc_offset = 25;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
}

9
src/mainboard/starlabs/starfighter/variants/rpl/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_6core =
&cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
@ -41,15 +38,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 30;
cfg->tcc_offset = 30;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 25;
cfg->tcc_offset = 25;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
}

9
src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c
View file

@ -13,9 +13,6 @@ void devtree_update(void)
{
config_t *cfg = config_of_soc();
struct soc_intel_common_config *common_config;
common_config = chip_get_common_soc_structure();
struct soc_power_limits_config *soc_conf_4core =
&cfg->power_limits_config[ADL_N_041_6W_CORE];
@ -36,15 +33,15 @@ void devtree_update(void)
switch (get_power_profile(PP_POWER_SAVER)) {
case PP_POWER_SAVER:
performance_scale -= 50;
common_config->pch_thermal_trip = 30;
cfg->tcc_offset = 30;
break;
case PP_BALANCED:
performance_scale -= 25;
common_config->pch_thermal_trip = 25;
cfg->tcc_offset = 25;
break;
case PP_PERFORMANCE:
/* Use the Intel defaults */
common_config->pch_thermal_trip = 20;
cfg->tcc_offset = 20;
break;
}