mb/cwwk/adl: Fix HDMI, PCIe CLKREQ, EC, TPM
- Update VBT to fix HDMI
- Enable ITE environment controller
- Enable PTT fTPM
- Disable s0ix, it never worked and will crash if used
- Set CLKREQ# based on register values from vendor firmware
- Set pmc_gpe0_dw{0-3} to fix "Duplicate GPE DW register values"
Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716
Signed-off-by: Brandon Weeks <bweeks@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
parent
3c96687c2c
commit
0e775bc390
3 changed files with 42 additions and 21 deletions
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@ -5,10 +5,12 @@ if BOARD_CWWK_ADL_N
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select CRB_TPM
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select DRIVERS_UART_8250IO
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select FSP_TYPE_IOT
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_INTEL_PTT
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_ALDERLAKE_PCH_N
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select SUPERIO_ITE_IT8613E
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Binary file not shown.
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@ -1,6 +1,8 @@
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chip soc/intel/alderlake
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register "s0ix_enable" = "true"
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
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register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
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@ -14,45 +16,49 @@ chip soc/intel/alderlake
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register "pch_pcie_rp[PCH_RP(1)]" = "{
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.clk_src = 0,
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.clk_req = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
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}"
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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.clk_req = 1,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_L0S,
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}"
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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.clk_req = 2,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_L0S,
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}"
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 3,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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.clk_req = 3,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_L0S,
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}"
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register "pch_pcie_rp[PCH_RP(11)]" = "{
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.clk_src = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_DISABLE,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_L0S,
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}"
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register "pch_pcie_rp[PCH_RP(12)]" = "{
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.clk_src = 4,
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.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
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.pcie_rp_aspm = ASPM_DISABLE,
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.flags = PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
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.pcie_rp_aspm = ASPM_L0S,
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}"
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# Enable EDP in PortA
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register "ddi_portA_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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device domain 0 on
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device ref igpu on end
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device ref dtt on end
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device ref crashlog off end
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device ref xhci on end
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device ref shared_sram on end
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@ -63,21 +69,34 @@ chip soc/intel/alderlake
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device ref pcie_rp11 on end
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device ref pcie_rp12 on end # M.2 E key port
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device ref pch_espi on
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x003c0a01"
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register "gen3_dec" = "0x000c0081"
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chip superio/ite/it8613e
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register "FAN2.mode" = "FAN_SMART_SOFTWARE" # CPU_FAN
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register "FAN3.mode" = "FAN_SMART_SOFTWARE" # SYS_FAN
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device pnp 2e.0 off end
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device pnp 2e.1 on # COM 1
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device pnp 2e.1 on # COM 1
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io 0x60 = 0x3f8
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irq 0x70 = 0x4
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irq 0xf0 = 0x1
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end
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device pnp 2e.4 off end # Environment Controller
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device pnp 2e.5 off end # Keyboard
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device pnp 2e.6 off end # Mouse
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device pnp 2e.7 off end # GPIO
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device pnp 2e.a off end # CIR
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0x0a30
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io 0x62 = 0x0a20
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irq 0x70 = 0x00
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irq 0x71 = 0x80
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end
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device pnp 2e.5 off end # Keyboard
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device pnp 2e.6 off end # Mouse
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device pnp 2e.7 off end # GPIO
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device pnp 2e.a off end # CIR
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end
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end
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device ref hda on end
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device ref smbus on end
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chip drivers/crb
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device mmio 0xfed40000 on end
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end
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end
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end
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