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mb/starlabs/starbook/mtl: Don't configure MUX pins

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These were incorrectly copied from Alder Lake so remove them
as they are not correct nor needed.

Change-Id: I70708212c4652ed77c875242340c30edf5b935a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86651
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-02-28 14:18:19 +00:00 • committed by Matt DeVillier
commit 172853a8ce
2 changed files with 0 additions and 15 deletions
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1
src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk
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@ -7,4 +7,3 @@ romstage-y += romstage.c
ramstage-y += devtree.c
ramstage-y += gpio.c
ramstage-y += hda_verb.c
ramstage-y += ramstage.c

14
src/mainboard/starlabs/starbook/variants/mtl/ramstage.c
View file

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <option.h>
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
{
/*
* FSP defaults to pins that are used for LPC; given that
* coreboot only supports eSPI, set these pins accordingly.
*/
supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
}