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mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue

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Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on vell and verify that the device
suspends to S0ix.

Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86646
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Pranava Y N 2025-02-28 17:07:05 +05:30 • committed by Subrata Banik
commit 6df02490a7
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/google/brya/variants/vell/overridetree.cb
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@ -191,6 +191,13 @@ chip soc/intel/alderlake
.clk_src = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "srcclk_pin" = "1"
device generic 0 on end
end
end
device ref tbt_pcie_rp3 on end
device ref cnvi_wifi on