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mb/google/brya/gladios: Enable RTD3 for SSD to resolve S0ix issue

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Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on gladios and verify that the device
suspends to S0ix.

Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86648
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Pranava Y N 2025-02-28 17:11:07 +05:30 • committed by Subrata Banik
commit 26d494b57a
1 changed files with 7 additions and 0 deletions
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7
src/mainboard/google/brya/variants/gladios/overridetree.cb
View file

@ -149,6 +149,13 @@ chip soc/intel/alderlake
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "srcclk_pin" = "0"
device generic 0 on end
end
probe STORAGE STORAGE_NVME
end #NVMe
device ref tbt_pcie_rp0 off end