mb/google/nissa/var/dirks: Configure TCSS port 1 to USB Type-A
Configure EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose TCSS port 1 to USB Type-A (Document Number: 742076) USB Ports for dirks: (FRONT) USBA 10G x 3 (REAR) USBA 10G x 2 + USBC 10G x 1 BUG=b:389391653 TEST=none. Change-Id: Ib227995cde8d871ff58c89ccb09221226640a7e6 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85991 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
36fd23d143
commit
d43ac436da
2 changed files with 13 additions and 0 deletions
|
|
@ -4,3 +4,4 @@ bootblock-y += gpio.c
|
|||
romstage-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
ramstage-y += ramstage.c
|
||||
|
|
|
|||
12
src/mainboard/google/brya/variants/dirks/ramstage.c
Normal file
12
src/mainboard/google/brya/variants/dirks/ramstage.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
/*Enable Type C port1 convert to Type A*/
|
||||
params->EnableTcssCovTypeA[1] = 1;
|
||||
/* PCH xchi port number for Type C port1 port mapping */
|
||||
params->MappingPchXhciUsbA[1] = 2;
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue