Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`acpigen_soc_get_tx_gpio` will put the result into Local0, rather than
emitting it as a byte so adjust the function accordingly.
Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This resource is applicable to S0, as it can be used to reset
the wireless and for RTD3, so change it from S5.
Change-Id: I9ae710ef452c717ec414324d2847bf3218fd62d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:383032918#comment1
BUG=b:383032918
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85535
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
We use ALC3204 as HDA codec on uldrenite, add the verb table
by Realtek.
BUG=b:374203133
TEST=emerge-nissa coreboot
Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a generic optimization to calculate a machine-word-sized
"wide sum" for the ipchksum() algorithm. This is often not as
efficient as handcrafted assembly (about half as fast on arm64 and
x86_32, about the same speed on x86_64), but likely still much better
than nothing on architectures that we don't have handcrafted assembly
for.
Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80304
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MediaTek booker (the customized ARM CI-700) is a high-performance
interconnect architecture designed for multi-core processor systems,
providing high bandwidth, low latency data transfer. And booker mainly
uses CHI protocol, but doesn't support coherence (which is achieved
through ACP solution). Additionally, the booker also uses other
protocols such as AXI, which translates CHI transactions into EMI's AXI
transactions.
Currently, the mt8196 booker only uses the functions of SLC CMO routing.
If downstream SLC needs CMO command propagation from the DSU, it is
needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of
each SBSX node in order to propagate the CMO command.
Increase the bootblock size from 75K to 78K to support booker.
TEST=build pass, check boot log with:
[booker_init] AP hash rule: 0xbe00.
BUG=b:317009620
Signed-off-by: Dehui Sun <dehui.sun@mediatek.corp-partner.google.com>
Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Once the MPLL has been initialised, convert the timings from the SPD to
be in DCLKs, which is what the hardware expects. In addition, calculate
the values for tREFI and tXP.
Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64184
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Move PCU specific code into separate files:
- PCUs registers are now locked by the PCI driver final call
- set_bios_init_completion() is not part of PCU1 driver
- Integrate config_reset_cpl3_csrs() into PCU driver
TEST: Still boots on ocp/tiogapass.
Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85316
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Match function name "init" with "remove" by renaming all
*_breakpoint_disable() to *_breakpoint_remove().
Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85540
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to debug stack smashing add a write breakpoint to the
stack canary (at _stack or _car_stack) and print the IP when the
stack canary is written.
TEST: Wrote to address _stack in ramstage and got the EIP of the
code that smashed the stack canary.
Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following functions are added:
_create_buffer_field
acpigen_write_create_buffer_byte_field
acpigen_write_create_buffer_word_field
acpigen_write_create_buffer_dword_field
acpigen_write_create_buffer_qword_field
These functions are to generate:
CreateByteField (<namestring> , offset, <field name>)
CreateWordField (<namestring> , offset, <field name>)
CreateDWordField (<namestring> , offset, <field name>)
CreateQWordField (<namestring> , offset, <field name>)
NOTE:
There are set of acpigen_write_create_[byte/word/dword/qword]_field
functions already, but the field can only be created from Arg[n] or
Local[n] variable objects. A Name object must be first assigned to such
variable. The new functions here will allow us to create field directly
from Name object.
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85197
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit enables the Dynamic Platform and Thermal Framework (DPTF)
for the fatcat board.
DPTF is a system management framework that allows the board to
dynamically adjust its power and thermal settings based on the system
load and thermal conditions. This can help to improve the board's
performance and battery life.
The following changes were made to enable DPTF:
- Added the Intel DPTF driver to the board's Kconfig file.
- Overrode the default DPTF settings in the fatcat variant
overridetree.cb file.
- Enabled the DPTF policy on the baseboard.
Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Enable the DRIVERS_GENERIC_BAYHUB_LV2 Kconfig option to apply
errata for the Bayhub PCIe-based SD controller (device ID 0x8621).
BUG=b:376019977
TEST=Built and booted google/fatcat with a functional x1 slot.
Change-Id: Iebc5bb73d895e8b20c47a924c6665c6ad289d1c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The following GPIOs are already implemented in fw_config.c based on
CBI values:
- GPP_A08: X1_PCIE_SLOT_PWR_EN
- GPP_B25: X1_SLOT_WAKE_N
- GPP_D19: X1_DT_PCIE_RST_N
This change removes the redundant GPIO definitions from gpio.c.
BUG=b:376019977
TEST=Able to build and boot google/fatcat with functional x1 slot.
Change-Id: I56c6fd3ea8b9e58933548543d195621da94c882e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528
Reviewed-by: Divagar Mohandass <divagar.mohandass@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s.
BUG=b:376156567
TEST=Boot to OS and then check link speed.
Use command: lspci -s 02:00.0 -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85533
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)) returns
the register content and should not be compared with
PCI_ITSS_PIR(0) which is an address offset. By now, we assume the
returned PIR is always effective and usable.
Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85284
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add const qualifer for itss_get_on_chip_dev_pirq and
itss_soc_get_on_chip_dev_pir so that these ops could be used for
both struct device * input and const struct device * input.
Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will
be executed in common pch/lockdown firstly. Remove xeon_sp layer
lpc_lockdown_config() to avoid duplication.
The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c:
static void platform_lockdown_config(void *unused)
{
int chipset_lockdown;
chipset_lockdown = get_lockdown_config();
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);
/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);
...
}
Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85286
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop function fast_spi_set_vcl as the same code already exists
as fast_spi_vscc0_lock() and is already run on xeon_sp.
Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
acpigen_write_PRT_pre_routed should support _PRT reporting for
both domains and PCI root ports.
TESTED=Build and boot on intel/avenuecity CRB
_PRT will be correctly reported and IRQ routing missing error in
dmesg will disappear
[ 40.406496] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.413799] pci 0000:17:00.0: PCI INT A: no GSI
[ 40.418965] pcieport 0000:14:08.0: can't derive routing for PCI INT A
[ 40.426272] ast 0000:18:00.0: PCI INT A: no GSI
Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85151
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: <yuchi.chen@intel.com>
PCI devices not pre-routed will have their interrupt line left as
0. Skip these devices in _PRT reporting.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: I3d51b75eb0fd1c4ca877f6ac884de2742e7f9630
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85152
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: <yuchi.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 8fb91783ffa9:
2024-08-23 14:45:12 +0200 - (Merge "fix(intel): add in missing ECC register" into integration)
to commit id 15e5c6c91d48:
2024-12-05 16:00:37 +0100 - (Merge changes I00d2de7b,I5ec82646 into integration)
This brings in 512 new commits.
Change-Id: I18b5bae0f48b2794a40d8c9e9cba8c69639669f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.
BUG=b:374205496
TEST=Boot to OS and then check link speed.
Use command: lspci -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch corrects the conditional inclusion of the `ufs.asl` file in
the southbridge ACPI configuration.
Previously, the inclusion of `ufs.asl` was incorrectly dependent on the
`MAINBOARD_USES_IFD_GBE_REGION` Kconfig option. This prevented the UFS
ACPI entry from being included in the DSDT when
`MAINBOARD_USES_IFD_GBE_REGION` was disabled, causing issues with
booting from UFS media.
This commit fixes the issue by ensuring that `ufs.asl` is included
based on the `SOC_INTEL_PANTHERLAKE_U_H` Kconfig option, which correctly
reflects the presence of UFS hardware.
This change ensures that the UFS ACPI device is correctly enumerated and
available to the operating system.
BUG=b:382243957
TEST=Able to verify UFS ACPI device is available inside DSDT table.
Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for the optional TPM. When GPP_A22 is low a TPM is
installed.
TEST: Found a working TPM 2.0 SLB9670 on ocp/tiogapass.
Change-Id: I970033981a265eb0094bc91fc070487b34972a5a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85510
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPX uses the same PCH as SKX does, thus it has the same ACPI timer
timer and PM2 control fields as SKX.
Copy the code from skx to cpx to reduce code differences. Allows to
merge both codebases into one.
Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the supported mainboards have a 8042 compatible chip,
thus drop it from the common code.
When such board is added it can update fadt->iapc_boot_arch
by installing a mainboard_fill_fadt() method.
Change-Id: I40cafcec57dd49399ce449700c81a1f27c1ded99
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85507
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both CPX and SKX always enable EIST, thus the generic
generate_p_state_entries() method can be used to generate _PSS.
This also reduces code differences between skx and cpx and allows
to merge both codebases into one.
Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The board has 24 slots for DDR4 ECC RDIMMs and it has 2 CPU sockets,
where each is connected to 12 DIMMs. Every socket supports up to
6 channels, thus every channel is connected to 2 DIMMs.
Implement mainboard_dimm_slot_exists accordingly to advertise all slots
as SMBIOS type 17.
TEST: Found all installed DIMMs advertised through SMBIOS on
ocp/tiogapass.
Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85318
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not use a define for a PCI register to lock a MSR.
The defines will be moved in the following commit to it's own header,
preventing the use in CPX CPU init.
Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move CPU init closer to other SoC and CPX.
FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.
FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL
Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO
Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree
Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.
TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in
ACPI C6, no boot delay or hung tasks could be found.
Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented
in non-Lite CSE SKUs. Original CL [1] adding this feature also says
that, but at that point the feature was validated for CSE Lite only.
Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to
have it compile for mainboards without CSE Lite.
TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with
SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`:
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 34,000
945:CSE started to handle ICC configuration 172,000 (138,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000)
991:Die Management Unit (DMU) load completed 360,000 (46,000)
0:1st timestamp 385,844 (25,844)
11:start of bootblock 398,796 (12,952)
12:end of bootblock 402,099 (3,302)
[...]
[1]: https://review.coreboot.org/c/coreboot/+/59507
Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This change fixes building NovaCustom V540TU, which previously errored
out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition.
Replace soc/gpio_defs.h with gpio.h which includes everything we need,
same as it was done for ADL in change 71266, and other SoCs.
TEST=Build and boot NovaCustom V540TU
Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds soundwire codec addresses in the devicetree to
calculate addresses for the ACPI table instead of previous kconfig which
allows single board to select multiple soundwire codecs at runtime
based on FW_CONFIG.
BUG=b:368495490
TEST=build coreboot image and boot on google fatcat. Disassemble
SSDT and confirm ACPI entries are correct for alc7xx device.
Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85440
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
