Introduce a mechanism so that coreboot can provide a list of options to
post-coreboot code. The options are grouped together into forms and
have a meaning name and optional help text. This can be used to let
payloads know which options should be displayed in a setup menu,
for instance. Although this system was written to be used with edk2,
it has been designed with flexibility in mind so that other payloads
can also make use of this mechanism. The system currently lacks a way
to describe where to find option values.
This information is stored in a set of data structures specifically
created for this purpose. This format is known as CFR, which means
"coreboot forms representation" or "cursed forms representation".
Although the "forms representation" is borrowed from UEFI, CFR can
be used in non-UEFI scenarios as well.
The data structures are implemented as an extension of cbtables records
to support nesting. It should not break backwards compatibility because
the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children
records. The concept of record nesting is borrowed from the records for
CMOS options. It is not possible to reuse the CMOS records because they
are too closely coupled with CMOS options; using these structures would
needlessly restrict more capable backends to what can be done with CMOS
options, which is undesired.
Because CFR supports variable-length components, directly transforming
options into CFR structures is not a trivial process. Furthermore, CFR
structures need to be written in one go. Because of this, abstractions
exist to generate CFR structures from a set of "setup menu" structures
that are coreboot-specific and could be integrated with the devicetree
at some point. Note that `struct sm_object` is a tagged union. This is
used to have lists of options in an array, as building linked lists of
options at runtime is extremely impractical because options would have
to be added at the end of the linked list to maintain option order. To
avoid mistakes defining `struct sm_object` values, helper macros exist
for supported option types. The macros also provide some type checking
as they initialise specific union members.
It should be possible to extend CFR support for more sophisticated
options like fan curve points. Feedback about this is highly
appreciated.
Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74121
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since QEMU commit 728b923f548d
("target/arm: Do memory type alignment check when translation enabled")
alignment is checked for device memory. That causes exceptions during
bootup of coreboot trying to load things (e.g. stages) from the memory
mapped flash.
To fix it the memory mapped flash region will be marked as MA_MEM
(normal memory) instead of MA_DEV (device memory). Technically that
isn't 100% correct, but avoids having to write a custom memory mapped
flash driver that checks for alignment on all accesses. Since it is
emulation and therefore always normal memory anyway, there shouldn't be
any side effects.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I98bd1a18495e3d153ce53abec8686c7871ee12c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85147
Reviewed-by: David Milosevic <David.Milosevic@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The MiTAC Computing Whitestone2 O-RAN CU/DU Edge Server is a compact
and highly efficient 1U rackmount solution designed for edge computing
in O-RAN (Open Radio Access Network) environments. Featuring support
for the 4th Gen Intel® Xeon® Scalable Processor Edge Enhanced Product
Family, it delivers robust performance with a single socket (LGA-4677)
that supports up to 205W TDP. The server provides excellent memory
capabilities with 8 DDR5 RDIMM slots supporting 4400 MHz speeds across
8 channels per CPU.
Working:
- All eight DIMM slots
- Serial port to emit spam
- POST code display
- Front USB 2.0 port
- Front Intel E810 CAM1 (25Gbps x 4)
- Front Intel E810 CAM2 (25Gbps x 4 / 10Gbps x 8)
- M.2 2280/22110 slot x 2 (Gen3 x4)
- Flashing internally with flashrom
Untested for now (i.e. should work, will eventually test):
- Riser PCIe Gen.4 x16 slots x 2 (FHHL)
Others:
- The board boots to Ubuntu 22.04.2 (5.15.0-1032-realtime) with all
40 cores (Intel 5433n) available.
- FlexRAN 23.11 + DPDK 22.11.1 + ACC200 O-RU + O-DU long-run test
pass.
Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905
Signed-off-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85532
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the schematic_20241203, configure USB ports and their
mappings.
BUG=b:380789023
TEST=emerge-nissa coreboot
Change-Id: I8fa3bf958faaf17b35e33fe93e2a11e0d2eb48d6
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85582
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nissa project fw branch is more suitable for compatibility with unknown, so the compatible methods of wifi and ssd are replaced.
BUG=b:383675207
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Rauru reference design has SD card interfaces, so we have to configure
it in ramstage.
Implement msdc.c (memory and SD Card controller) to place the SD card
drivers.
This implementation is based on chapter 10.3 in MT8196 Functional
Specification.
TEST=Build pass
BUG=b:317009620
Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85564
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug.
Rename VLPCFG_BASE to VLP_CFG_BASE.
TEST=Build pass, When we encounter a bus hang and HW watchdog triggers
a reset to the platform, the tracker will print the
latched information:
[INFO ] **Dump %s aw debug register start**
[INFO ] xxxxxx, 0x1c600000, 0x0, 63
This means that the 63rd entry latch accessing 0x1c600000 has a bus
timeout.
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84929
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMinfra is the Multimedia Infrastructure. All the Multimedia modules
depend on it. This file adds some initial settings for MMinfra.
Test=Build pass
BUG=b:317009620
Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.corp-partner.google.com>
Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enable IDT_IN_EVERY_STAGE in qemu to easily debug HW breakpoints.
TEST: Can use breakpoints in pre RAM stages to debug invalid
memory accesses on QEMU.
Change-Id: If4a386d1adc788ff717899027881590b7c8b3369
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Make use of exception handling in every stage. Additionally this
enables breakpoints in all stages, making NULL dereferences and
stack overflows easier to detect.
TEST: Stack canary exceptions are seen in romstage on ibm/sbp1.
Change-Id: I8a9f12b9ae041ce47c14f2ef7f09b029d408260e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85569
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced in commit 0351872731
("arch/x86: Add breakpoint to stack canary").
romstage_main writes to the stack-canary, but since that's expected
temporarily disable the breakpoint. This only caused a warning on
platforms that do select IDT_IN_EVERY_STAGE, since those install the
stack canary breakpoint.
TEST: No more exceptions are printed in romstage when IDT_IN_EVERY_STAGE
is enabled.
Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The mainboard code relies on IPMI communication with the BMC.
Since the x86 and BMC start booting at the same time on ACPI G3
exit and the x86 is a bit faster, wait for the BMC to signal it's
done booting by pulling GPP_F4 low.
Fixes lots of error messages in coreboot about not working IPMI:
[ERROR] wait_ibf timeout!
[ERROR] IPMI START WRITE failed
[ERROR] ipmi_kcs_send_message failed
TEST: Once GPP_F4 is low IPMI communication over the KCS is also
working on ocp/tiogapass.
The log contains the line:
[DEBUG] BMC ready after 125560 ms
Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85492
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 559910 Intel Connectivity Platforms BIOS
Guideline revision 8.2 and 9.2 specifications, both revision 0 and 1
are supported and share the same structure.
BUG=b:346600091
Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85586
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit rewrites the CPU topology initialization code to simplify
it and make it more maintainable.
The previous code used a complex set of if-else statements to
initialize the CPU topology based on the CPUID leaves that were
supported. This has been replaced with a simpler and more readable
function that follows the Intel Software Developer Manual
recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if
available.
The new code removes the need for separate functions to handle the
topology initialization for different CPUID leaves. It uses a static
array of bitfield descriptors to store the APIC ID descriptor
information for each level of the CPU topology. This simplifies the
code and makes it easier to add new levels of topology in the future.
The code populates the node ID based on the package ID, eliminating
the need for an extra function call.
Change-Id: Ie9424559f895af69e79c36b919e80af803861148
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage
hook and introduce early_pch_init() to do PCH init in romstage before
FSP-M runs.
Move PCH specific code into early_pch_init and call it from common code.
Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85505
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no
official bit in the IFD to disable it. The device is disabled
early to:
1. Prevent FSP from seeing the device being present. It could keep
an internal state that the device is working.
2. Prevent FSP-M from trying to detect codecs. This would increase
boot time.
3. Prevent FSP from becoming confused or crash when the device is
suddently missing as disabled by a ramstage PCI driver.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85496
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the debug code as there were unexplainable stack corruptions
detected on some platforms.
No problems were observed on:
- QEMU
- Xeon-SP
Change-Id: I1f1b9f01af7fbb0c19becf6ea53d436898584c5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply ISH_FW_VERSION in Kconfig to improve boot time.
It won't do some ISH init task without the config on UFS sku and
cause boot to kernel time over 1.55 sec from G3 boot.
BUG=b:364971947
BRANCH=firmware-brox-16080.B
TEST=cbmem -c | grep "ISH version" -> ISH version: 5.4.2.7780
Boot to OS on jubilant, run bootperf test of G3 boot.
Confirm the test result is pass.
Change-Id: I31db0925a81b6ec68ee6afcb262e540ba7db206a
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update header files for FSP for Meteor Lake platform to version 4122_21,
previous version being 3471_91.
FSPS:
1. Added UPD's ThcMode, ThcWakeOnTouch
2. Reserved bit changes
FSPM:
1 Added PchHdaSubSystemIds
BUG=b:329548127
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I4a1164060f7e91f8fa4ada60421bf87fb17ad541
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84656
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Route IRQ for on-chip end-points only (e.g. 00:1f.4
i801_smbus)
IRQ routing for devices under root ports needs additional
swizzle per decided by root port configurations, which will
postponed to later till there is actual usage.
2. Route IRQ based on FSP programmed end-point device ID <->
PIRQ mapping.
TESTED=Build and boot on intel/avenuecity CRB
Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch introduces logging for the ELOG_TYPE_FW_CSE_SYNC event. This
event logs data related to CSE synchronization, along with the relevant
boot stage information.
BUG=b:305898363
TEST=boot verified on google/rex0 and google/rex64
Change-Id: I4d6d3c4e07ab8677feb6a8acf8d4c6604ab704b8
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85218
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new event log type, ELOG_TYPE_FW_CSE_SYNC. The
purpose of this event type is to log successful completion of CSE
synchronization.
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
Change-Id: Id73fa3a77e5fbbae5c61dfb30ae26b4ba3dca6ab
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85217
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ImguClkOutEn parameters are required in pantherlake, therefore,
avoid disabling the IMGU CLKOUT FSP UPDs.
BUG=b:381044394
TEST=Able to see FSP-M UPDs for google/fatcat where IMGU CLKOUTs are
not disabled with this patch.
Change-Id: Ieb022e6dc0b64106ff30f56cd17f9f219276785f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85588
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and
`DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options
for the Pantherlake SOC.
These options are causing false positive stack overflow detections,
leading to unnecessary debugging.
w/o this patch:
stack corruption before for verstage and romstage early.
Failed to create address zero instruction fetch breakpoint
Failed to create stack canary breakpoint
...
...
Stack corruption detected at rip: 0xf983007a
Stack corruption detected at rip: 0xf983007a
Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85584
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Format bare URLs as links so that they are rendered as hyperlinks
instead of plain text.
Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85433
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in memory config based on the schematic_20241203.
BUG=b:380476928, b:380789023
TEST=emerge-nissa coreboot
Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85542
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This change enables the GPP_F9 GPIO, which controls the SLP_S0_GATE_R
signal and subsequently the SYS_SLP_S0IX_L signal.
By enabling GPP_F9 early in the boot process, we ensure the panel is
powered on correctly and able to render the eSOL message.
BUG=b:372737590
TEST=Verified panel power-on by observing eSOL during build on
google/marasov.
Change-Id: I727a72d9583575b2bbebe2c3b75c980170dd36b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The GPP_F23/ISH_GP_9A pin receives the lid open/close signal from
SMC_LID. This pin is not utilized in the AP firmware stack; however
the ISH firmware requires this signal for its tablet mode support.
Therefore, we configure this pin as an ISH GPIO.
BUG=b:370984186
TEST=Build and flash CB; run ISH main firmware; read this pin and
verified it returned the correct value.
fatcat-rev257 ~ # ectool --name=cros_ish gpioget lid_open
GPIO lid_open = 1
Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to its
SRAM space and then enable it.
It takes 20 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x62c00 size 0x21ab6 in mcache @0xfffdd314
mtk_init_mcu: Loaded (and reset) sspm.bin in 20 msecs (256212 bytes)
TEST=can see the sspm logs.
BUG=b:372173976
Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0
Signed-off-by: Kenji Yu <kenji.yu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The patch disables Tccold Handshake to prevent possible display
flicker issue for jubilant board. Please refer to Intel doc#723158
for more information.
BUG=b:383433239
BRANCH=firmware-brox-16080.B
TEST=Boot to OS on jubilant, verify the display is without flicker.
Change-Id: I4f22067b81fa1b1b9addd7d1f49de59136d221c0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85555
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
After modified the settings, it could be met the time sequence for
this ILIT2901 touchscreen specification via our EE's measurements.
1. ILIT2901 Specification: ILI2901A-A202 Data Sheet_V1.2_20240128.pdf.
2. Double delay RST time to 12ms.
3. F/W calibration delay time is about 700ms after RST high.
The tuned firmware version is 005c_0700.0000.0000.0006.bin.
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Verified the sequence correctly by EE.
Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Implement PMIF driver for communication between SoC and PMIC. Develop
SPMI driver for communication over the SPMI bus. Add necessary
configurations and base addresses to support PMIF.
TEST=build pass, check boot log with:
[INFO ] mtk_pmif_init: SPMI_MASTER_1, 0
[INFO ] mtk_pmif_init: SPMI_MASTER_0, 0
BUG=b:317009620
Change-Id: I232015f45735ee5278b09d0352410617a1565177
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85126
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change simply replaces 0x80 with a top level constant called
ACPI_NOTIFY_CROS_EC_MKBP. There are no functional changes.
BUG=b:343288326
TEST=Build
Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Add GBTR Method, which gets the state of the RF Kill pin. Unlike
the VGPIO, this can be used for both CNVi and full PCI wireless
cards.
Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
