haswell NRI: Initialise MPLL
Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64184 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Angel Pons
Lean Sheng Tan
parent
41c2e1685e
commit
4a4ad2b1e6
6 changed files with 259 additions and 1 deletions
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@ -1,5 +1,7 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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romstage-y += init_mpll.c
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romstage-y += io_comp_control.c
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romstage-y += raminit_main.c
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romstage-y += raminit_native.c
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romstage-y += spd_bitmunching.c
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219
src/northbridge/intel/haswell/native_raminit/init_mpll.c
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src/northbridge/intel/haswell/native_raminit/init_mpll.c
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@ -0,0 +1,219 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <commonlib/bsd/clamp.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <types.h>
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#include "raminit_native.h"
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static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
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{
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const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
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if (ctrl->base_freq == 100)
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return clamp_u32(7, mult, 12);
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if (ctrl->base_freq == 133)
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return clamp_u32(3, mult, 10);
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die("Unsupported base frequency\n");
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}
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static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
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{
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/** TODO: Haswell supports up to DDR3-2600 **/
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if (ctrl->tCK <= TCK_1200MHZ) {
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ctrl->tCK = TCK_1200MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 1200;
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} else if (ctrl->tCK <= TCK_1100MHZ) {
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ctrl->tCK = TCK_1100MHZ;
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ctrl->base_freq = 100;
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ctrl->mem_clock_mhz = 1100;
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} else if (ctrl->tCK <= TCK_1066MHZ) {
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ctrl->tCK = TCK_1066MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 1066;
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} else if (ctrl->tCK <= TCK_1000MHZ) {
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ctrl->tCK = TCK_1000MHZ;
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ctrl->base_freq = 100;
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ctrl->mem_clock_mhz = 1000;
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} else if (ctrl->tCK <= TCK_933MHZ) {
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ctrl->tCK = TCK_933MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 933;
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} else if (ctrl->tCK <= TCK_900MHZ) {
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ctrl->tCK = TCK_900MHZ;
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ctrl->base_freq = 100;
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ctrl->mem_clock_mhz = 900;
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} else if (ctrl->tCK <= TCK_800MHZ) {
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ctrl->tCK = TCK_800MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 800;
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} else if (ctrl->tCK <= TCK_700MHZ) {
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ctrl->tCK = TCK_700MHZ;
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ctrl->base_freq = 100;
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ctrl->mem_clock_mhz = 700;
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} else if (ctrl->tCK <= TCK_666MHZ) {
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ctrl->tCK = TCK_666MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 666;
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} else if (ctrl->tCK <= TCK_533MHZ) {
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ctrl->tCK = TCK_533MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 533;
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} else if (ctrl->tCK <= TCK_400MHZ) {
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ctrl->tCK = TCK_400MHZ;
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ctrl->base_freq = 133;
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ctrl->mem_clock_mhz = 400;
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} else {
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ctrl->tCK = 0;
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ctrl->base_freq = 1;
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ctrl->mem_clock_mhz = 0;
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return;
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}
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if (!pll_ref100 && ctrl->base_freq == 100) {
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/* Skip unsupported frequency */
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ctrl->tCK++;
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normalize_tck(ctrl, pll_ref100);
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}
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}
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#define MIN_CAS 4
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#define MAX_CAS 24
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static uint8_t find_compatible_cas(struct sysinfo *ctrl)
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{
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printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
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const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
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const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
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if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
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printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
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ctrl->tCK++;
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return 0;
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}
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for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
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printk(RAM_DEBUG, "%u ", cas);
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if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
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printk(RAM_DEBUG, "OK\n");
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return cas;
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}
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}
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return 0;
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}
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static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
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{
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/** TODO: Honor all possible PLL_REF100_CFG values **/
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uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
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printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
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printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
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uint8_t selected_cas;
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while (true) {
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/* Round tCK up so that it is a multiple of either 133 or 100 MHz */
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normalize_tck(ctrl, pll_ref100);
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if (!ctrl->tCK) {
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printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
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return RAMINIT_STATUS_MPLL_INIT_FAILURE;
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}
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selected_cas = find_compatible_cas(ctrl);
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if (selected_cas)
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break;
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ctrl->tCK++;
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}
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printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
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printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
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printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", selected_cas);
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ctrl->multiplier = get_mem_multiplier(ctrl);
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return RAMINIT_STATUS_SUCCESS;
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}
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enum raminit_status initialise_mpll(struct sysinfo *ctrl)
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{
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if (ctrl->tCK > TCK_400MHZ) {
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printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
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ctrl->tCK = TCK_400MHZ;
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}
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while (true) {
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/*
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* On fast and S3 flows, MPLL frequency is already decided and
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* has to match training data. So, skip finding the frequency.
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*
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* Also skip this when the MPLL is already locked. This can be
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* the case if retrying raminit for some reason e.g. fast flow
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* failed or the margins post power training are below minima.
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*/
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/** FIXME: This terribleness ignores failure modes in fast / S3 flows **/
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if (!ctrl->qclkps) {
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const enum raminit_status status = find_cas_tck(ctrl);
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if (status)
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return status;
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}
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/*
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* Unlike previous generations, Haswell's MPLL won't shut down if the
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* requested frequency isn't supported. But we cannot reinitialize it.
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* Another different thing: MPLL registers are 4-bit instead of 8-bit.
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*/
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/** FIXME: Obtain current clock frequency if we want to skip this **/
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//if (mchbar_read32(MC_BIOS_DATA) != 0)
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// break;
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uint32_t mc_bios_req = ctrl->multiplier;
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if (ctrl->base_freq == 100) {
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/* Use 100 MHz reference clock */
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mc_bios_req |= BIT(4);
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}
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mc_bios_req |= BIT(31);
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printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
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printk(BIOS_DEBUG, "MPLL busy... ");
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mchbar_write32(MC_BIOS_REQ, mc_bios_req);
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for (unsigned int i = 0; i <= 5000; i++) {
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if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
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printk(BIOS_DEBUG, "done in %u us\n", i);
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break;
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}
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udelay(1);
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}
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if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
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printk(BIOS_DEBUG, "did not lock\n");
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/* Verify locked frequency */
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const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
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printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
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if ((mc_bios_data & 0xf) >= ctrl->multiplier)
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break;
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printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
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ctrl->tCK++;
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}
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if (!ctrl->mem_clock_mhz) {
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printk(BIOS_ERR, "Could not program MPLL frequency\n");
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return RAMINIT_STATUS_MPLL_INIT_FAILURE;
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}
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printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
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ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
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printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
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ctrl->qclkps = ctrl->mem_clock_fs / 2000;
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printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
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return wait_for_first_rcomp();
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}
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@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <commonlib/bsd/clamp.h>
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#include <console/console.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <timer.h>
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#include <types.h>
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#include "raminit_native.h"
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enum raminit_status wait_for_first_rcomp(void)
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{
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struct stopwatch timer;
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stopwatch_init_msecs_expire(&timer, 2000);
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do {
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if (mchbar_read32(RCOMP_TIMER) & BIT(16))
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return RAMINIT_STATUS_SUCCESS;
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} while (!stopwatch_expired(&timer));
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printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
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return RAMINIT_STATUS_POLL_TIMEOUT;
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}
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@ -20,7 +20,8 @@ struct task_entry {
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};
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static const struct task_entry cold_boot[] = {
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{ collect_spd_info, true, "PROCSPD", },
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{ collect_spd_info, true, "PROCSPD", },
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{ initialise_mpll, true, "INITMPLL", },
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};
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/* Return a generic stepping value to make stepping checks simpler */
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@ -24,6 +24,8 @@ enum raminit_status {
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RAMINIT_STATUS_SUCCESS = 0,
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RAMINIT_STATUS_NO_MEMORY_INSTALLED,
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RAMINIT_STATUS_UNSUPPORTED_MEMORY,
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RAMINIT_STATUS_MPLL_INIT_FAILURE,
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RAMINIT_STATUS_POLL_TIMEOUT,
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RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
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};
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@ -83,10 +85,19 @@ struct sysinfo {
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uint8_t rankmap[NUM_CHANNELS];
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uint8_t rank_mirrored[NUM_CHANNELS];
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uint32_t channel_size_mb[NUM_CHANNELS];
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uint8_t base_freq; /* Memory base frequency, either 100 or 133 MHz */
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uint32_t multiplier;
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uint32_t mem_clock_mhz;
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uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */
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uint32_t qclkps; /* Quadrature clock period in picoseconds */
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};
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void raminit_main(enum raminit_boot_mode bootmode);
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enum raminit_status collect_spd_info(struct sysinfo *ctrl);
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enum raminit_status initialise_mpll(struct sysinfo *ctrl);
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enum raminit_status wait_for_first_rcomp(void);
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#endif
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@ -13,6 +13,8 @@
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#define MC_INIT_STATE_G 0x5030
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#define MRC_REVISION 0x5034 /* MRC Revision */
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#define RCOMP_TIMER 0x5084
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#define MC_LOCK 0x50fc /* Memory Controller Lock register */
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#define GFXVTBAR 0x5400 /* Base address for IGD */
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@ -61,6 +63,7 @@
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#define BIOS_RESET_CPL 0x5da8 /* 8-bit */
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#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */
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#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */
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#define SAPMCTL 0x5f00
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