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mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

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The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.

BUG=b:374205496
TEST=Boot to OS and then check link speed.
     Use command: lspci -vv | grep 'LnkSta'

     Before
     LnkSta: Speed 8GT/s (downgraded), Width x1
     After
     LnkSta: Speed 5GT/s (downgraded), Width x1

Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
David Wu 2024-12-06 15:41:12 +08:00 • committed by Subrata Banik
commit 861413b295
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brya/variants/riven/overridetree.cb
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@ -487,6 +487,7 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_pcie_speed = SPEED_GEN2,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"