This patch corrects the EC sync IRQ configuration logic to properly
handle different ocelot board variants:
1. Update conditional compilation in ec.h to exclude OCELOTMCHP and
OCELOTMCHP4ES variants from EC_ENABLE_SYNC_IRQ, as these boards do
not have the EC sync IRQ connected.
2. Restructure GPIO definitions in gpio.h to:
- Set EC_SYNC_IRQ to 0 (not connected) for OCELOTMCHP, OCELOTMCHP4ES,
variants.
- Enable EC_SYNC_IRQ on GPP_E08_IRQ for OCELOT, OCELOT4ES, OCELOTITE,
and OCELOTITE4ES variants.
3. Configure GPP_E08 pad appropriately in gpio.c:
- Set as NC (not connected) for OCELOTMCHP variants.
- Configure as APIC interrupt for other variants that support EC sync
IRQ functionality.
BUG=NONE
TEST=Build and boot on Ocelot variants.
Change-Id: I96e92ed9d6fa5b586ab9c0faf73d08b55abe4795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89459
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from
350ms to 330ms. Validation on Prade shows the controller initializes
reliably within the reduced timing. It will be able to complete the
following steps before vccs on.
1. TP Reset
2. Get HID Description
3. HID Reset/HID Power On
4. Get Report Descriptor/Get Feature Report
Verification results are in b/455053468 comment#3
BUG=b:455053468
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence
Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.
Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add config `MEDIATEK_DSI_CPHY` to enable the MIPI C-PHY interface on
mt8189, including necessary register definitions and integrating with
the common MIPI driver, dsi_register_v2.
BUG=b:433422905,b:428854543
TEST=Check display initialization log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iac6c1b6d47331b63e7b45157bd60da93f104b0ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89620
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data
rate calculations, timing configurations, and register settings for
C-PHY operation.
To improve code reusability, the D-PHY and C-PHY specific
implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`,
respectively.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
(cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add a new member 'flags' to the panel structure in panel.h, and define
`PANEL_FLAG_CPHY` to indicate C-PHY interface support. This change
enables panel drivers to check and handle C-PHY panels.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=build passed
Signed-off-by: Bincai Liu bincai.liu@mediatek.corp-partner.google.com
Signed-off-by: Vince Liu vince-wl.liu@mediatek.corp-partner.google.com
Change-Id: I4c35ad2cb6fc2289598ae47b3abf1c6c706dad42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 7d8e105420 ("mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge
board GA-H77M-D3H"), adding this board, initially enabled igd and
peg10 in the device tree, but later, during review, Patchset 10
removed those lines of the device tree entirely, disabling onboard
and PCIe graphics in the port as ultimately submitted.
This commit re-adds these lines to the device tree, enabling both -
thanks to nic3-14159 for spotting the issue. I have confirmed both
now work on my GA-H77M-D3H.
TEST=Confirm IGD outputs as configured in SeaBIOS and Linux (with
CONFIG_ONBOARD_VGA_IS_PRIMARY), same for PCIe GPU (running option
ROMs).
$ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core
processor DRAM Controller (rev 09)
00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200
v2/3rd Gen Core processor Graphics Controller (rev 09)
...
With a monitor connected to the onboard DVI:
$ cat /sys/class/graphics/fb0/virtual_size
1920,1080
Change-Id: I248827b92d9f14cedbbd666d533764b5f152cf29
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Internal flashing of the entire chip is possible from vendor firmware
by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is
connected to one of the unused pins of the PCIE1 slot.
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.17.0 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)
Untested:
- Intel VBIOS
- Front USB headers
- Other fans
- LED headers
- eSATA, Toslink
- PCIE1 (x1) slot
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add firmware configuration support for SPD (Serial Presence Detect)
selection on Intel PTLRVP boards. This change allows dynamic memory
configuration based on fw_config fields instead of relying solely on
board ID detection.
BUG=None
TEST=Build and verify SPD selection works correctly on PTLRVP boards
with different memory configurations.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3cc45ad9813bef09718fe679bfafb700024586f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88255
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The hardware is mostly identical to the already supported Thinkpad
T480s. Aside from the CPU (KBL vs SKL), major hardware differences are
GPIO pins routed out to a classical docking station connector, and the
lack of support for dedicated GPUs.
A tricky aspect of this machine is that it fails to enumerate PCIe
devices when using a truncated Intel ME firmware even when retaining
the MFS partition [1]. I suspect that the PCIe clock generators are set
up in some other part of the ME firmware.
The VBT (intelvbttool) as well as GPIO register dumps (inteltool) was
obtained from the latest stock BIOS 1.55/N1WET76W. GPIO, USB and PCIe
port assignments have been cross-checked against the publicly available
schematics (Thorpe-2).
The patches were validated on a laptop with part number 20JT-S16E00 in
conjunction with a non-truncated deguarded Intel ME firmware [2].
A cursory hardware test (video, wifi, audio, network, reboot, etc.) has
everything working as expected (debian 13).
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
[2] deguard commit 497732f8b2e3bdc699c0fbc6713b6afbaef7506a
Change-Id: I113b31484a634b7c1acdba5f74e5eef050d4ede6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89638
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
note: The entire patch was created using AI (besides commit-msg)
Change-Id: I0f80d1d8cd67b26a4ec1014584b5486254115839
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Co-authored-by: aider (openrouter/anthropic/claude-sonnet-4) <aider@aider.chat>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89677
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kodkod variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:451760650
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_KODKOD
Change-Id: I8bbea4444d65e57b98bf9c8a621ff548abb8aece
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89679
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If using clangd for development, your .clangd file is almost
certainly specific to your environment, and should be gitignored,
same as e.g. .vscode/
Change-Id: I3388d14f381aa9f68be9806652514a741fad49c9
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.
Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. Add DB_1C_5G 8 on DB_USB overridetree.
2. Also disable LTE-related GPIOs based on fw_config when system
was DB_1C_5G.
BUG=b:445338278
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Check 5G LTE module detectable by command # mmcli -m a.
Change-Id: I3d525d9de151427d38485882117b59939b9da5c7
Signed-off-by: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89606
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG= b:435094908
TEST= verify headset jack works properly.
Change-Id: Ibd5271e496a9ca841498b17a5746e300f9557078
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89605
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.
The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.
BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.
Without this CL -
USB2 key doesn't work for C1.
Verified HS1 functionality by turning on L14B from coreboot.
Before USB insertion:
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Added USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Removed USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A .gitkeep file is an unofficial convention used in Git to keep and
track empty directories, as Git does not track empty folders by default.
This could be needed when one mainboard variant has an include directory
but another doesn't. If the directory is added to the include, it could
be easier to just create an empty include directory with a .gitkeep file
in it to keep things from failing.
Change-Id: I34b2ffa4d748d82e26867ecd5b9149301300e6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
4608KB (4.5MB) to incorporate the QTEE FW and its config files.
TEST =Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I69ce0f3cff2cae110a21417245c425ee8bcf1e6c
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rename `common/dsi.c` to `common/dsi_common.c` since this file is used
by all SoCs. Rename `common/mtk_dsi_common.c` to `common/dsi_v1.c`, as
this file serves as the v1 implementation for all SoCs except mt8173.
These changes help clarify file usage and improve code readability.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie711175434febce149a22742d78132842a6ec329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89655
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Now that the PinMux is correctly configured, everything works
as it should without having FSP touch the GPIOs.
Change-Id: Ieec678594f49f3aa003ade29aad85b24ec03f1ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
We use winbond, gigadevice spi flash, and will use spi flash from other vendors in the future, so we have enable all SPI Flash drivers.
BUG=b:442967024
BRANCH=None
TEST=emerge-bluey coreboot chromeos-bootimage
Change-Id: Icb9eeea90e924d412ad782ccf1ac390707f27314
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89641
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design
BUG=b:446813859
TEST=emerge-fatcat coreboot
Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.
Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.
BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.
BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.
Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Move mtk_dsi_reset() from mtk_mipi_dphy.c to mtk_dsi_common.c so that it
can also be used when using the C-PHY interface, improving code reuse.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I3f080127af4411584f66e307f7d2b13abbb051bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89619
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Recent GCC versions (>=12) warn about out-of-bounds accesses when
writing through *(volatile uint8_t *)dest in endian.h.
This is a false positive since these pointers intentionally alias
hardware/physical memory.
Change-Id: Ia47aa1214998dbc17bd4a58f7d996bcc6fff7b6a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The amdfw.rom will be divided into 3 parts:
PSP Level 1, PSP Level 2A, PSP Level 2B.
The two ISHs are close to L1 and can be combined as a CBFS module.
To do that, move the new_psp_dir for L1 and L2 to separated branches.
The final sequence is EFS, PSP L1, ISH A, ISH B, PSP L2A, BIOS L2A,
PSP L2B, BIOS L2B.
TEST=Google/Skyrim
Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Select HAVE_ACPI_TABLES & PCI for QEMU riscv virt machine mainboard. Add
an empty dsdt.asl to fit current build process, but it will not actually
be used since QEMU has its own method of providing DSDT blob.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".
Change-Id: If8c9b5d86adb69afdcb4bf320d6353b2b2acfb31
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89562
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the CS42L43 codec on SoundWire link 3 and the CS35L56
amplifiers on SoundWire link 2.
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
{
Device (SW20)
{
Name (_ADR, 0x00023001FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
Device (SW21)
{
Name (_ADR, 0x00023101FA355601) // _ADR: Address
Name (_DDN, "Right Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
BUG=b:444122406, b:444302600
TES=emerge-lapis coreboot
Change-Id: Ic73d705655bdc0a4a8140feafa28aceb2fc25ad3
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot does not use the nds32le-elf toolchain at all, but it causes
build issues in the CI. So drop it from the default builds. It can
still be built by using buildgcc.
Change-Id: I5e5e5b6914265d6aff14c011062db268db4acf6b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89317
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a null pointer check to ensure that the SoC-specific
function to retrieve I2C bus speed is properly mapped before attempting
to call it. Without this check, systems may crash during boot when the
function pointer is not initialized. The issue occurs when the
touchscreen or touchpad is configured to use THC-I2C via CBI fw_config,
but the underlying SoC doesn't provide the required I2C speed function
implementation.
BUG=none
TEST=Boot Fatcat board to OS with CBI fw_config selecting touchscreen or
touchpad using THC-I2C. Verify no crash occurs during boot and touch
devices function properly.
Change-Id: Ib982f4435aa506f2b9203f81140366addc6559f3
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Originally, there were separate EC firmware builds for the smart
battery (SB) and non-SB versions of the starlite_adl board, but those
have long since been unified. Squash the board variants into a single
board which supports both SB and non-SB boards.
Adjust the board description to reflect that it will support both the
existing N200 and upcoming N355 flavors.
TEST=build/boot starlite_adl on both SB and non-SB boards, verify
battery and all other features function normally.
Change-Id: I2461a094f2455ce333132ffa9f2f83967ae0e927
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR setup menu option to enable/disable the USB micro-SD card
reader, but restrict it to newer boards which use the MXC
accelerometer, as those boards have the card reader on USB2 port 4,
rather than shared with the detachable keyboard on port 3.
TEST=build/boot on starlite_adl boards with and without the MXC
accelerometer, verify only boards with it have the CFR option
to disable the card reader shown, and that the option works
as expected.
Change-Id: I9255d008c6f322d01390ed9f19e4e963cf04eeb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Create the ruby variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:446771934
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_RUBY
2. Run part_id_gen tool without any errors
Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
