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Venkateshwar S 35d4b3f2f4 arch/arm64: Support to load QTEE firmware in x1P42100
This patch adds support to load QTEE firmware in X1P42100. A new
Kconfig 'ARM64_HAS_SECURE_OS_PAYLOAD' has been introduced to support
packing the QTEE firmware as a CBFS payload type. Based on this
configuration, the QTEE firmware is packed either as a stage or payload
type in CBFS.

In X1P42100, the QTEE FW is packed as a CBFS payload type, as its
memory regions are non-contiguous across system IMEM and DDR.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Ensure loading of the QTEE firmware in the appropriate regions.

[INFO ]  CBFS: Found 'fallback/secure_os' @0xff1c0 size 0x2ac188
[DEBUG]  read SPI 0xd2f218 0x2ac188: 225876 us, 12405 KB/s, 99.240 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 2802056 bytes, hash algo 2, HW
                acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0x1468f000 memsize 0x2000 srcaddr
                0x9f804280 filesize 0x2000
[DEBUG]  Loading Segment: addr: 0x1468f000 memsz: 0x0000000000002000
                filesz: 0x0000000000002000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x1468f000, 14691000, 0x14691000) <- 9f804280
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0x14691000 memsize 0x2000 srcaddr
                0x9f806280 filesize 0x2000
[DEBUG]  Loading Segment: addr: 0x14691000 memsz: 0x0000000000002000
                filesz: 0x0000000000002000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x14691000, 14693000, 0x14693000) <- 9f806280
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0xd8087000 memsize 0x12b000 srcaddr
                0x9f808280 filesize 0x12b000
[DEBUG]  Loading Segment: addr: 0xd8087000 memsz: 0x000000000012b000
                filesz: 0x000000000012b000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8087000, d81b2000, 0xd81b2000) <- 9f808280
[DEBUG]  Loading segment from ROM address 0x9f80414c
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd81b2000 memsize 0x14000 srcaddr
                0x9f933280 filesize 0x14000
[DEBUG]  Loading Segment: addr: 0xd81b2000 memsz: 0x0000000000014000
                filesz: 0x0000000000014000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd81b2000, d81c6000, 0xd81c6000) <- 9f933280
[DEBUG]  Loading segment from ROM address 0x9f804168
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd81c6000 memsize 0xb3000 srcaddr
                0x9f947280 filesize 0xb3000
[DEBUG]  Loading Segment: addr: 0xd81c6000 memsz: 0x00000000000b3000
                filesz: 0x00000000000b3000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd81c6000, d8279000, 0xd8279000) <- 9f947280
[DEBUG]  Loading segment from ROM address 0x9f804184
[DEBUG]    BSS 0xd8279000 (4096 byte)
[DEBUG]  Loading Segment: addr: 0xd8279000 memsz: 0x0000000000001000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8279000, d8279000, 0xd827a000) <- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d8279000 memsz:
                0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd82e6000 memsize 0x5d000 srcaddr
                0x9f9fa280 filesize 0xe000
[DEBUG]  Loading Segment: addr: 0xd82e6000 memsz: 0x000000000005d000
                filesz: 0x000000000000e000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd82e6000, d82f4000, 0xd8343000) <- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d82f4000 memsz:
                0x000000000004f000
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    BSS 0xd8343000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8343000 memsz: 0x0000000000010000
[DEBUG]  Loading Segment: addr: 0xd8279000 memsz: 0x0000000000001000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8279000, d8279000, 0xd827a000) <- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d8279000 memsz:
                0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd82e6000 memsize 0x5d000 srcaddr
                0x9f9fa280 filesize 0xe000
[DEBUG]  Loading Segment: addr: 0xd82e6000 memsz: 0x000000000005d000
                filesz: 0x000000000000e000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd82e6000, d82f4000, 0xd8343000) <- 9f9fa280
[DEBUG]  Clearing Segment: addr: 0x00000000d82f4000 memsz:
                0x000000000004f000
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    BSS 0xd8343000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8343000 memsz: 0x0000000000010000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8343000, d8343000, 0xd8353000) <- 9fa08280
[DEBUG]  Clearing Segment: addr: 0x00000000d8343000 memsz:
                0x0000000000010000
[DEBUG]  Loading segment from ROM address 0x9f8041d8
[DEBUG]    BSS 0xd8353000 (65536 byte)
[DEBUG]  Loading Segment: addr: 0xd8353000 memsz: 0x0000000000010000
                filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8353000, d8353000, 0xd8363000) <- 9fa08280
[DEBUG]  Clearing Segment: addr: 0x00000000d8353000 memsz:
                0x0000000000010000
[DEBUG]  Loading segment from ROM address 0x9f8041f4
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd836a000 memsize 0x1000 srcaddr
                0x9fa08280 filesize 0x1000
[DEBUG]  Loading Segment: addr: 0xd836a000 memsz: 0x0000000000001000
                filesz: 0x0000000000001000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd836a000, d836b000, 0xd836b000) <- 9fa08280
[DEBUG]  Loading segment from ROM address 0x9f804210
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0xd836b000 memsize 0x99000 srcaddr
                0x9fa09280 filesize 0x99000
[DEBUG]  Loading Segment: addr: 0xd836b000 memsz: 0x0000000000099000
                filesz: 0x0000000000099000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd836b000, d8404000, 0xd8404000) <- 9fa09280
[DEBUG]  Loading segment from ROM address 0x9f80422c
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd8404000 memsize 0x3000 srcaddr
                0x9faa2280 filesize 0x3000
[DEBUG]  Loading Segment: addr: 0xd8404000 memsz: 0x0000000000003000
                filesz: 0x0000000000003000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8404000, d8407000, 0xd8407000) <- 9faa2280
[DEBUG]  Loading segment from ROM address 0x9f804248
[DEBUG]    data (compression=0)
[DEBUG]    New segment dstaddr 0xd8407000 memsize 0xb000 srcaddr
                0x9faa5280 filesize 0xb000
[DEBUG]  Loading Segment: addr: 0xd8407000 memsz: 0x000000000000b000
                filesz: 0x000000000000b000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0xd8407000, d8412000, 0xd8412000) <- 9faa5280
[DEBUG]  Loading segment from ROM address 0x9f804264
[DEBUG]    Entry Point 0x1468f000
[SPEW ]  Loaded segments

Change-Id: I5498f418ae7ccc4a8ad2ca05698da3e0a3ec5609
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89548
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-10-19 19:41:49 +00:00
3rdparty 3rdparty/qc_blobs: Update submodule to upstream main 2025-09-12 12:46:46 +00:00
configs config/builder/mitac: Hook up public FSP repo and microcode 2025-08-30 13:56:13 +00:00
Documentation drivers/ipmi: add Block Transfer (BT) interface 2025-10-16 12:16:43 +00:00
LICENSES LICENSES: Add LGPL 2.1 license 2024-02-18 01:56:38 +00:00
payloads Revert "libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX" 2025-10-14 09:58:49 +00:00
spd spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part 2025-09-24 14:49:31 +00:00
src arch/arm64: Support to load QTEE firmware in x1P42100 2025-10-19 19:41:49 +00:00
tests tests/imd: Fix invalid NULL comparison on uintptr_t 2025-09-30 11:55:53 +00:00
util amdfwtool: Move ISH before PSP L2 2025-10-19 19:41:34 +00:00
.checkpatch.conf .checkpatch.conf: Set max line length to 96 2024-12-04 07:36:22 +00:00
.clang-format Treewide: Fix incorrect SPDX license strings 2024-02-18 01:55:57 +00:00
.editorconfig .editorconfig: Add indent style & size of 2 spaces for shell 2023-12-20 22:30:33 +00:00
.gitignore .gitignore: Ignore payloads/libpayload/generated/ 2024-01-11 14:39:52 +00:00
.gitmodules .gitmodules: Ignore changes make by what-jenkins-does 2025-07-17 20:38:35 +00:00
.gitreview .gitreview: Update default branch from master to main 2023-12-23 16:44:31 +00:00
.mailmap
AUTHORS AUTHORS: Update list to 25.03 2025-05-08 22:32:29 +00:00
COPYING
gnat.adc drivers/intel/gma: Allow SPARK function with side effects 2024-03-01 18:46:30 +00:00
MAINTAINERS MAINTAINERS: Drop non-existant TPM files from VBOOT 2025-10-14 14:37:06 +00:00
Makefile Reland "tests: Allow specifying vboot source directory" 2025-09-16 15:04:07 +00:00
Makefile.mk Makefile.mk: Add support for mainboard vendor common code 2025-10-17 20:36:57 +00:00
README.md Documentation: Update internal URL's 2024-01-04 14:22:51 +00:00
toolchain.mk tree: Replace scan-build by clang-tidy 2025-07-01 01:12:32 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).

With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.

Source code

All source code for coreboot is stored in git. It is downloaded with the command:

git clone https://review.coreboot.org/coreboot.git.

Code reviews are done in the project's Gerrit instance.

The code may be browsed via coreboot's Gitiles instance.

The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.

Supported Hardware

The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.

For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.

Releases

Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.

All releases are available on the coreboot download page.

Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.

Build Requirements and building coreboot

The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.

To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.

That same page goes through how to use QEMU to boot the build and see the output.

Website and Mailing List

Further details on the project, as well as links to documentation and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://doc.coreboot.org/community/forums.html

Copyrights and Licenses

Uncopyrightable files

There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.

"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."

https://guides.lib.umich.edu/copyrightbasics/copyrightability

Similar terms apply to other locations.

These uncopyrightable files include:

  • Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
  • Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
  • Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.

As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.

If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.

Copyrights

The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.

Licenses

Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.

Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.

Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.

The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.

The Software Freedom Conservancy

Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.