Call the `report_memory_config()` and `setup_sdram_meminfo()` functions,
which were factored out into shared raminit code in previous patches. As
the SPD data is not readily available where `setup_sdram_meminfo()` gets
called, add a function to get it from the saved data, as it is available
in a global context. Technically speaking, the "mighty ctrl" variable is
also static (thus global), but it is only meant to be used within native
raminit code and is only static to avoid nuking the stack (it is huge).
Change-Id: Ia2c0946f55748e38bb5ccb5cb06721aeb77527e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89600
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `report_memory_config()` function to shared raminit code, both
to deduplicate the code and to allow native raminit to make use of it.
Change-Id: I8b3c695c0a266634a42b0303e4f1ea699301c26b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89599
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `setup_sdram_meminfo()` function to shared raminit code
to deduplicate it as well as to allow native raminit to make use
of it, which will be done in a follow-up.
When consolidating the functions, the only functional difference
is that the Broadwell MRC.bin path reports memory frequencies in
MHz whereas the Haswell MRC.bin path reports them in MT/s. Since
this data is used to populate SMBIOS tables, which expect memory
frequencies in MT/s, using MT/s is the right choice.
Given that SPD data is handled differently in the three RAM init
implementations (Haswell MRC, Broadwell MRC, native raminit), we
have to abstract the SPD data pointers a bit. This is done using
an array of pointers.
While we're at it, add some TODO comments to note limitations of
the code. The idea is to fix those in follow-up commits.
Change-Id: I1f81bf18a9e856d80f8e4d7bda65089e999957f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reconfigure I2C controller settings to disable I2C1 and enable I2C6
for the mc_rpl1 mainboard. This change reflects the updated hardware
configuration requirements.
Changes:
- Disable I2C controller 1
- Enable I2C controller 6
TEST=Build and boot tested on mc_rpl1 mainboard.
Verified I2C6 functionality and confirmed I2C1 is disabled with
`lspci -v | grep -A 5 "Serial bus controller"`. The output
confirms that I2C6 (PCI 00:10.0) is enabled and I2C1 (PCI 00:15.1)
is disabled because it is absent.
```
00:10.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #2 (rev 01)
Subsystem: Intel Corporation Alder Lake-P Serial IO I2C Controller
Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 4
Memory at 80a12000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [80] Power Management version 3
Capabilities: [90] Vendor Specific Information: Len=14 <?>
```
Change-Id: I4867062743ee10b34f94a1e588a10115b553a16e
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Test=Change fan mode on byte_adl in edk2 and verify correct value
is written to the EC memory using `ectool -d`
Change-Id: I93d4be663a059abb973ad6abf2e60d40f56ed6c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Pujjoga and pujjogatwin projects are both going to be single RAM device, so add single ram configuration.
Schematic version: 500E_GEN4S_ADL_N_MB_250920
Below log show the device can recognize the single dram.
[INFO ] SPD: module type is LPDDR5X
[INFO ] SPD: module part number is H9JCNNNBK3MLYR-N6E
[INFO ] SPD: banks 8, ranks 1, rows 16, columns 11, density 16384 Mb
[INFO ] SPD: device width 16 bits, bus width 16 bits
[INFO ] SPD: module size is 2048 MB (per channel)
[INFO ] Device only supports one DIMM. Disable all other memory
channels except first two on each memory controller.
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x76fff000 254 entries.
[DEBUG] IMD: root @ 0x76ffec00 62 entries.
BUG=b:445629015
BRANCH=none
TEST=Build and boot to OS. Verify functions work.
Change-Id: I22e8335432e6e65bd1640bf6a6dec03691e3462e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89221
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure MMU for framebuffer region only when framebuffer region
exists (i.e., REGION_SIZE(framebuffer) > 0). Otherwise, the MMU would
raise assertion.
[INFO ] Mapping address range [0x0000040000000:0x0000240000000) as cacheable | read-write | non-secure | normal
[INFO ] Mapping address range [0x0000040000000:0x0000040100000) as non-cacheable | read-write | non-secure | normal
[DEBUG] Backing address range [0x0000040000000:0x0000080000000) with new L2 table @0x020da000
[DEBUG] Backing address range [0x0000040000000:0x0000040200000) with new L3 table @0x020db000
[INFO ] Mapping address range [0x0000000000000:0x0000000000000) as non-cacheable | read-write | non-secure | normal
[EMERG] ASSERTION ERROR: file 'src/arch/arm64/armv8/mmu.c', line 194
BUG=b:454457496
TEST=The assertion does not occur.
Change-Id: I8ab17bd289cd41a4568fddff2e556e5e49b1e6a4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Increase the ME region by 4KiB to match the IFD that is used for
both the Alder Lake and Twin Lake versions.
Change-Id: I22fa2388ed5660b959815be00029c07cac2b5244
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89761
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch corrects the EC sync IRQ configuration logic to properly
handle different ocelot board variants:
1. Update conditional compilation in ec.h to exclude OCELOTMCHP and
OCELOTMCHP4ES variants from EC_ENABLE_SYNC_IRQ, as these boards do
not have the EC sync IRQ connected.
2. Restructure GPIO definitions in gpio.h to:
- Set EC_SYNC_IRQ to 0 (not connected) for OCELOTMCHP, OCELOTMCHP4ES,
variants.
- Enable EC_SYNC_IRQ on GPP_E08_IRQ for OCELOT, OCELOT4ES, OCELOTITE,
and OCELOTITE4ES variants.
3. Configure GPP_E08 pad appropriately in gpio.c:
- Set as NC (not connected) for OCELOTMCHP variants.
- Configure as APIC interrupt for other variants that support EC sync
IRQ functionality.
BUG=NONE
TEST=Build and boot on Ocelot variants.
Change-Id: I96e92ed9d6fa5b586ab9c0faf73d08b55abe4795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89459
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from
350ms to 330ms. Validation on Prade shows the controller initializes
reliably within the reduced timing. It will be able to complete the
following steps before vccs on.
1. TP Reset
2. Get HID Description
3. HID Reset/HID Power On
4. Get Report Descriptor/Get Feature Report
Verification results are in b/455053468 comment#3
BUG=b:455053468
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence
Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.
Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add config `MEDIATEK_DSI_CPHY` to enable the MIPI C-PHY interface on
mt8189, including necessary register definitions and integrating with
the common MIPI driver, dsi_register_v2.
BUG=b:433422905,b:428854543
TEST=Check display initialization log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iac6c1b6d47331b63e7b45157bd60da93f104b0ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89620
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data
rate calculations, timing configurations, and register settings for
C-PHY operation.
To improve code reusability, the D-PHY and C-PHY specific
implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`,
respectively.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
(cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add a new member 'flags' to the panel structure in panel.h, and define
`PANEL_FLAG_CPHY` to indicate C-PHY interface support. This change
enables panel drivers to check and handle C-PHY panels.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=build passed
Signed-off-by: Bincai Liu bincai.liu@mediatek.corp-partner.google.com
Signed-off-by: Vince Liu vince-wl.liu@mediatek.corp-partner.google.com
Change-Id: I4c35ad2cb6fc2289598ae47b3abf1c6c706dad42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 7d8e105420 ("mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge
board GA-H77M-D3H"), adding this board, initially enabled igd and
peg10 in the device tree, but later, during review, Patchset 10
removed those lines of the device tree entirely, disabling onboard
and PCIe graphics in the port as ultimately submitted.
This commit re-adds these lines to the device tree, enabling both -
thanks to nic3-14159 for spotting the issue. I have confirmed both
now work on my GA-H77M-D3H.
TEST=Confirm IGD outputs as configured in SeaBIOS and Linux (with
CONFIG_ONBOARD_VGA_IS_PRIMARY), same for PCIe GPU (running option
ROMs).
$ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core
processor DRAM Controller (rev 09)
00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200
v2/3rd Gen Core processor Graphics Controller (rev 09)
...
With a monitor connected to the onboard DVI:
$ cat /sys/class/graphics/fb0/virtual_size
1920,1080
Change-Id: I248827b92d9f14cedbbd666d533764b5f152cf29
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Internal flashing of the entire chip is possible from vendor firmware
by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is
connected to one of the unused pins of the PCIE1 slot.
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.17.0 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)
Untested:
- Intel VBIOS
- Front USB headers
- Other fans
- LED headers
- eSATA, Toslink
- PCIE1 (x1) slot
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add firmware configuration support for SPD (Serial Presence Detect)
selection on Intel PTLRVP boards. This change allows dynamic memory
configuration based on fw_config fields instead of relying solely on
board ID detection.
BUG=None
TEST=Build and verify SPD selection works correctly on PTLRVP boards
with different memory configurations.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3cc45ad9813bef09718fe679bfafb700024586f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88255
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The hardware is mostly identical to the already supported Thinkpad
T480s. Aside from the CPU (KBL vs SKL), major hardware differences are
GPIO pins routed out to a classical docking station connector, and the
lack of support for dedicated GPUs.
A tricky aspect of this machine is that it fails to enumerate PCIe
devices when using a truncated Intel ME firmware even when retaining
the MFS partition [1]. I suspect that the PCIe clock generators are set
up in some other part of the ME firmware.
The VBT (intelvbttool) as well as GPIO register dumps (inteltool) was
obtained from the latest stock BIOS 1.55/N1WET76W. GPIO, USB and PCIe
port assignments have been cross-checked against the publicly available
schematics (Thorpe-2).
The patches were validated on a laptop with part number 20JT-S16E00 in
conjunction with a non-truncated deguarded Intel ME firmware [2].
A cursory hardware test (video, wifi, audio, network, reboot, etc.) has
everything working as expected (debian 13).
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
[2] deguard commit 497732f8b2e3bdc699c0fbc6713b6afbaef7506a
Change-Id: I113b31484a634b7c1acdba5f74e5eef050d4ede6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89638
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
note: The entire patch was created using AI (besides commit-msg)
Change-Id: I0f80d1d8cd67b26a4ec1014584b5486254115839
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Co-authored-by: aider (openrouter/anthropic/claude-sonnet-4) <aider@aider.chat>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89677
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kodkod variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:451760650
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_KODKOD
Change-Id: I8bbea4444d65e57b98bf9c8a621ff548abb8aece
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89679
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If using clangd for development, your .clangd file is almost
certainly specific to your environment, and should be gitignored,
same as e.g. .vscode/
Change-Id: I3388d14f381aa9f68be9806652514a741fad49c9
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.
Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. Add DB_1C_5G 8 on DB_USB overridetree.
2. Also disable LTE-related GPIOs based on fw_config when system
was DB_1C_5G.
BUG=b:445338278
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Check 5G LTE module detectable by command # mmcli -m a.
Change-Id: I3d525d9de151427d38485882117b59939b9da5c7
Signed-off-by: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89606
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG= b:435094908
TEST= verify headset jack works properly.
Change-Id: Ibd5271e496a9ca841498b17a5746e300f9557078
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89605
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.
The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.
BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.
Without this CL -
USB2 key doesn't work for C1.
Verified HS1 functionality by turning on L14B from coreboot.
Before USB insertion:
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Added USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Removed USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A .gitkeep file is an unofficial convention used in Git to keep and
track empty directories, as Git does not track empty folders by default.
This could be needed when one mainboard variant has an include directory
but another doesn't. If the directory is added to the include, it could
be easier to just create an empty include directory with a .gitkeep file
in it to keep things from failing.
Change-Id: I34b2ffa4d748d82e26867ecd5b9149301300e6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
4608KB (4.5MB) to incorporate the QTEE FW and its config files.
TEST =Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I69ce0f3cff2cae110a21417245c425ee8bcf1e6c
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rename `common/dsi.c` to `common/dsi_common.c` since this file is used
by all SoCs. Rename `common/mtk_dsi_common.c` to `common/dsi_v1.c`, as
this file serves as the v1 implementation for all SoCs except mt8173.
These changes help clarify file usage and improve code readability.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie711175434febce149a22742d78132842a6ec329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89655
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Now that the PinMux is correctly configured, everything works
as it should without having FSP touch the GPIOs.
Change-Id: Ieec678594f49f3aa003ade29aad85b24ec03f1ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
We use winbond, gigadevice spi flash, and will use spi flash from other vendors in the future, so we have enable all SPI Flash drivers.
BUG=b:442967024
BRANCH=None
TEST=emerge-bluey coreboot chromeos-bootimage
Change-Id: Icb9eeea90e924d412ad782ccf1ac390707f27314
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89641
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design
BUG=b:446813859
TEST=emerge-fatcat coreboot
Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.
Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.
BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.
BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.
Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Move mtk_dsi_reset() from mtk_mipi_dphy.c to mtk_dsi_common.c so that it
can also be used when using the C-PHY interface, improving code reuse.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I3f080127af4411584f66e307f7d2b13abbb051bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89619
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Recent GCC versions (>=12) warn about out-of-bounds accesses when
writing through *(volatile uint8_t *)dest in endian.h.
This is a false positive since these pointers intentionally alias
hardware/physical memory.
Change-Id: Ia47aa1214998dbc17bd4a58f7d996bcc6fff7b6a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
