Configure SPI according to the mainboard wiring. Disable GSPI completely
as it is unused on this platform. Enable FSPI and configure it to
interface with the TPM device.
Implement TPM measured boot functionality starting from bootblock to
ensure secure boot chain validation from the earliest boot stage.
Change-Id: I89b60101c94393816b51154459f39bb22d5b976d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Enable UART0, UART1 and UART2 in the devicetree. Adjust current UART
console configuration from UART0 to UART2. Additionally, enable LPSS
UART for the coreboot console on UART2.
Change-Id: I4ba521b3edd6a37f726a256a26051d5ab9acadfc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88885
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A variant specific Kconfig file is introduced. This improves
configuration management by separating variant-specific options from the
baseboard.
Change-Id: I3760bf0ec2d16722ba99459244968ef2db249453
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Move the SOC-specific Kconfig options from the variant to the baseboard
configuration. This ensures all variants will inherit the correct SOC
selection.
This simplifies configuration and ensures consistency across variants.
Change-Id: Icf13ebd022dbe35f7c5deadfb425f1f9b572ed86
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
In total three USB ports are used:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
Overcurrent reporting is not supported for these ports.
Remove the appropriate UPDs in devicetree and move them to the
variant level to match the hardware configuration.
Change-Id: I9ab02780cfc11f88ddd2bb52bd7fbfb3fdd450ef
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard only uses I2C0 and I2C1. Disable all the others. Move I2C
configuration from baseboard to variant.
Change-Id: I0c554ea4da948bc96d6a392c39bcb07a25a79eb4
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88880
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard does not utilize CKLREQ signaling for PCIe. Only three
PCIe clock sources are used on this board. Configure the Root Ports
accordingly to hardware implementation.
Change-Id: If4241a05dd0c5df258d4a7018d71a21f7d314e69
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88879
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 and BE200 wifi sar table for pujjolo/pujjoquince
wifi sar config. Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_PUJJOLO_AX211 :0
WIFI_SAR_TABLE_PUJJOLO_BE200 :1
WIFI_SAR_TABLE_PUJJOQUINCE_AX211 :2
option WIFI_SAR_TABLE_PUJJOQUINCE_BE200 :3
BUG=b:428071905
Test=emerge-nissa coreboot
Change-Id: Iea8b32a19c4c2116afb5e5e4014dbc32e484ae3e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add fivr related setting based on schematics 500E_S3A0_TWL_MB_FVT_20250527.pdf
BUG=b:437881361
TEST=Build and boot to OS, check suspend funtion work fine using
suspend_stress_test -c 5 command.
Change-Id: I6c7f2807cc6a9c7c82e28d26205b33d068792522
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the lapis variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:438785495
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_LAPIS
2. Run part_id_gen tool without any errors
Change-Id: Iabcc673a1868cea1d8a650af213d583cc2e27c28
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Increase the CBFS cache in the memory layout of MediaTek Chromebook SoCs
to allow larger payloads like LinuxBoot to be loaded correctly.
TEST=Build and boot coreboot with LinuxBoot payload for
Google/Cherry/Tomato.
Change-Id: I4ce15e04cc19612ef1eed0fa0674ef8a7fd21fbe
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Use i2c_eeprom_read() to speed up reading the SPD EEPROMs.
TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
940:waiting for ME acknowledgment of raminit 116,514 (62,804)
After:
940:waiting for ME acknowledgment of raminit 110,212 (57,612)
Boots 5msec faster when MRC cache is present.
Change-Id: I500d7ff7a66b08b5036c0031e4fa20746d06df19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Users have requested to be able to disable the power LED, so add
this as an option.
Change-Id: I74da148c7891ab3dd5e5b692239670c9937ab302
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88890
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Booted on Lenovo X220 and found the UEFI menu working.
Change-Id: I194ff7b663c092c90882de4e7408b4c1e907984e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use udelay() over reading port 80h to delay CPU operation.
Since SMBUS runs at 100Khz a typical operation takes about
200usec or more to complete. Using udelay(1) doesn't delay
the boot for too long.
TEST=Booted on Lenovo X220. No additional boot delay was found.
Change-Id: Ied745927b1c54b53d7450b8e0c0a03d648a3ebba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be 65W to match the standard 65W GaN chargers.
Change-Id: I9a2be32b3b377090694cf23c4a4b85db47108c48
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88784
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.
This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.
TEST=Builds successfully for x1p42100.
Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes a bug in load_and_render_logo_to_framebuffer where the
logo_bottom_margin was only correctly applied to the NORMAL
orientations.
For other orientations, the margin was incorrectly applied, resulting
in the logo not being positioned as expected.
TEST=Able to see logo footer in alignment with the logo center while
booting google/felino.
Change-Id: Ia886ef5305166b1307fcf5b0acd12582b4b6ad80
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
@0x1485e340
[INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
supported for secdata_kernel v0, return 0
[INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
forbidden
[INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
@0x1485e7c0
```
Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.
Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add 2 memory parts in mem_parts_used.txt, and generate SPD id
for these parts.
1. H58G56CK8BX146 (Hynix)
2. MT62F2G32D4DS-023 WT:C (Micron)
BUG=b:422831379
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Ia6ee285f558a456c423586ccd7e970d14dd3cfea
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SSDs block the CPU from reaching PC10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
Disable GPP_F20 (EN_PP3300_SSD) and GPP_H23 (SRCCLKREQ#5) by fw_config
for Non-SSD sku.
BUG=b:435567235
TEST= emerge-brox coreboot
suspend_stress_test verify that the device suspends to S0ix.
suspend_stress_test w/o this CL
(with Kioxia PCIE Gen4 SSD KBG60ZNV512G)
Suspend failed, pc10 count did not increment from 0
Package C-States Now :
Package C2 : 26205917
Package C3 : 0
Package C6 : 0
Package C7 : 0
Package C8 : 0
Package C9 : 0
Package C10 : 0
Substate Residency
S0i2.0 0
S0i3.0 0
suspend_stress_test w/ this CL
Device suspends to S0ix.
Substate Residency
S0i2.0 0
S0i3.0 12020538
Change-Id: Iecffa89ae7865bc63b1b0dd974a439f35e9ca7f4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88771
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In the scenario of suspend, when the SPM firmware attempts to turn off
the VDDQ and VMDDR power supplies, the command sent is rejected by PMIF,
resulting in a system hang. The reason is that SPM simultaneously wrote
two registers (two bytes), while the original configuration only allowed
reading or writing one byte at a time.
Modify the maximum number of bytes that an SPMI user can read or write
in a single operation to meet the requirement of reading or writing 16
bits at once.
BUG=b:420874944
BRANCH=skywalker
TEST=2-byte R/W passed; suspend-resume verified successfully.
Change-Id: I46ace45564328c46ab340b74d73e3574957e36ef
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88790
Reviewed-by: Vince Liu <vince-wl.liu@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Niklaus Liu <niklaus.liu@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Some eDP panels assert HPD (Hot Plug Detect) after panel VCC is enabled,
typically around 200ms. To reduce boot time, this commit replaces the
original fixed 200ms delay with polling for the HPD status, shortening
the waiting period to approximately 70ms.
Once the HPD pin is detected high, an additional delay of around 1ms is
introduced to ensure the AUX channel is ready for EDID reading.
BUG=b:434574691,b:439535227,b:439476647
BRANCH=none
TEST=Check firmware display on Navi and Skywalker
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6702c79416700b44d4bfbc763b6fc6003feb69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.
Change-Id: I1d2761856e0c9bf9cc7045cc8e3af622582bd1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This script will warn and suggest fixes when a CB:<change-id> of an
already merged change is found in the commit message. This should
enforce the clarification that was added to the documentation in
CB:88776.
This script requires a JSON parser (i.e. jq) to parse Gerrit's
REST API[1]. While it may be possible to grep the values, we chose to
use a proper parser to ensure there would be no false-positives.
TEST=
Prepare a commit with the following commit message:
Here are some open changes: CB:88614 CB:88717 CB:87282
Here are some abandoned changes: CB:88413 CB:84504 CB:82136
Here are some merged changes: CB:88566 CB:88598 CB:88697
Here are some old merged commits: CB:1 CB:50 CB:950
Here are some wrong stuff: CL:100 CB:TEST CB:99999
The script produces the following result (may change in the future when
open changes are merged etc):
Using a change ID (CB:88566) for an already merged commit; please replace it with:
commit 21639c3771 ("mb/getac/p470: Use common gpio functions")
Using a change ID (CB:88598) for an already merged commit; please replace it with:
commit 05a38e2af3 ("mb/google/fatcat: Disable memory training progress bar")
Using a change ID (CB:88697) for an already merged commit; please replace it with:
commit 1da2f46db8 ("soc/intel/alderlake: Restore mem_init_override_channel_mask()")
Using a change ID (CB:1) for an already merged commit; please replace it with:
commit 140a990a61 ("Teach abuild to emit JUnit formatted build reports")
Using a change ID (CB:50) for an already merged commit; please replace it with:
commit 7c634ae8c1 ("msrtool: added support for Intel CPUs")
Using a change ID (CB:950) for an already merged commit; please replace it with:
commit c31384e62c ("Fix up Sandybridge C state generation code")
CB:99999 does not exist
[1] https://gerrit-review.googlesource.com/Documentation/rest-api.html
Change-Id: I1c72f739b1f47b1227ef1e158b1553aa56945d7e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This should address the following open action item from the coreboot
leadership meetings[1]:
> Add clarification to docs, "do not use gerrit change-id or CB: format
> in reference to already-merged patches".
[1] https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/YCA55MINAFK5M56OAUA2NMM7WDMDEGXI/
Change-Id: Ie742caca70e284254bb7f8a070c3a441b6a80c58
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88776
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extracted ICR wait logic into a new function 'icr_wait_timeout'.
Change-Id: Ie48899f7afb125061fd7efd44c83f5775c05d254
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses
after MPinit has removed the MTRR that was installed for postcar stage.
TEST=Booted on Lenovo X220 and measured using cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,391,520 (366,351)
After:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
Boots 156msec faster than before.
Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clear DF flag before invoking MOVS instruction to make sure it
increments %esi/%edi on each mov.
Change-Id: I209f50dec2003ea9846e5958d3e77b8979f338df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88796
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
from the project's Releases.md file:
* Prefer PCI IO allocations above 4Gig on 64bit capable machines.
* Multiple simultaneous USB keyboard and mouse support.
* Legacy support for internally generated ACPI tables has been removed.
* SeaVGABIOS support for VBE get/set palette data.
* Several bug fixes and code cleanups.
TEST=Successfully booted lenovo/t530
Change-Id: Ie1f0620ce46ebdafc84e8e13a79aa21c0526c235
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Config GPIO GPIO_AP_EDP_BKLTEN as output low. When skipping firmware
display, it can prevent leakage to GPIO_AP_EDP_BKLTEN and cause it
to be pulled up to a 0.6 V step.
BUG=b:438353560
BRANCH=none
TEST=skip fw display check GPIO_AP_EDP_BKLTEN Waveform
Change-Id: Icea1e035d62c89ea26bc58afa1d64ab8a448cc04
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88772
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
The alignment for several memory regions in the linker script was
specified using numeric values like `4096` or the hexadecimal `0x1000`.
Replace these values with the more readable `4K` shorthand. This change
improves consistency within the file and has no functional impact on
the generated binary.
TEST=Build and boot google/quenbi.
Change-Id: I28fdf3714d96f5e68a615d1550cf47d975ab5685
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently the SSD is preventing the system from entering S0ix sleep,
the system PKG C-State is stuck at PC3.
Intel RDC#642067 reveals while PEG60 is NDA but PEG62 is DA, need to
keep default PEG60 enabled and assign an unused CLKREQ# for port PEG60.
PEG60 is 00:06.0 (CPU PCIe Root port A).
PEG62 is 00:06.2 (CPU PCIe Root port B).
Caboc connectd SSD to PEG62 while PEG60 is not used.
As described above, follow RDC to assign the unused CLKREQ#5 for port
PEG60 and enable its related settings including pcie4_0, GPP_H23 NF2
as SRCCLKREQ#5, vGPIO and confirm the SSD can enter suspend.
BUG=b:435567235
TEST= emerge-brox coreboot
suspend_stress_test pass 100 cycles on SSD sku.
Measured the Boot/Resume time has improved.
seconds_power_on_to_kernel (Boot time)
Before/After 2.616/1.609
seconds_system_resume (Resume time)
Before/After s0ix error/0.338123
Change-Id: I26afeffd466cb2d8e0a0e4213214bde3b0a3b25b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
